spectre.awk: quote invalid identifiers (nodes, refdes)
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@ -36,9 +36,7 @@ BEGIN{
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}
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}
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# join split lines
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{
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if($0 ~ /^\/\/\/\/ begin user (architecture|header) code/) {
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user_code = 1
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}
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@ -120,6 +118,7 @@ function sign(x)
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function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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{
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gsub(/ *= */, "=")
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indent = $0
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sub(/[^ \t].*/, "", indent)
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if($0 ~/\/\/\/\/ end_element/){
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@ -154,7 +153,7 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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}
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# 20181208 do not process commented lines
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if($1 ~/^\//) {
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if($1 ~/^\/\//) {
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print
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return
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}
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@ -223,13 +222,19 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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if($0 ~ /^D/ ) sub(/PERI[ \t]*=/,"PJ=")
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if( $1 ~ /^\/\.(ipin|opin|iopin)/ ) {
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num=split($2,name,",")
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for(i=1;i<=num;i++) print $1 " " name[i]
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} else if( tolower($1) ~ /subckt/) {
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#### this is never executed: commented lines are processed and skipped above
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# if( $1 ~ /^\/\/\.(ipin|opin|iopin)/ ) {
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# num=split($2,name,",")
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# for(i=1;i<=num;i++) print $1 " " name[i]
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# } else
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if( tolower($1) ~ /subckt/) {
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# remove m=.. from subcircuit definition since m= is a multiplier not a param
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sub(/ m=[0-9]+/," ",$0)
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gsub(","," ",$0)
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for(i = 1; i <= NF; i++) {
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$i = q($i)
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}
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print $0
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} else {
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num = split($1, name, ",")
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@ -248,7 +253,7 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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}
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for(i=1;i<=num;i++)
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{
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printf "%s ", indent spiceprefix name[i]
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printf "%s ", indent spiceprefix q(name[i])
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for(j=2;j<=NF;j++)
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{
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@ -256,7 +261,7 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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# some CDL netlists have this: $SUB=?1 B where B is a node
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if($j !~ /^(.*=)?\?-?[0-9]+$/)
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{
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printf "%s ", $j # if not a node just print it
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printf "%s ", q($j) # if not a node just print it
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}
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else
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{
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@ -271,7 +276,7 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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for(l=0;l<nmult+0;l++)
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{
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ii=(l+nmult*(i-1))%arg_num[j]+1
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printf "%s ", arg_name[j,ii]
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printf "%s ", q(arg_name[j,ii])
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}
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}
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}
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@ -280,3 +285,15 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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}
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}
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function q(s)
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{
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if(s ~/.+=.+/) return s
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if(s ~ /^[()=]$/) return s
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if(s ~ /[^a-zA-Z0-9_$]/) {
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gsub(/'/, "''", s)
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s = "'" s "'"
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}
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return s
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}
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@ -274,9 +274,11 @@ function process( i,j, iprefix, saveinstr, savetype, saveanalysis)
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}
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}
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} else if( $1 ~ /^\*\.(ipin|opin|iopin)/ ) {
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num=split($2,name,",")
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for(i=1;i<=num;i++) print $1 " " name[i]
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#### this is never executed: commented lines are processed and skipped above
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# } else if( $1 ~ /^\*\.(ipin|opin|iopin)/ ) {
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# num=split($2,name,",")
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# for(i=1;i<=num;i++) print $1 " " name[i]
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} else if( tolower($1) ~ /\.subckt/) {
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# remove m=.. from subcircuit definition since m= is a multiplier not a param
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sub(/ m=[0-9]+/," ",$0)
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@ -133,7 +133,7 @@ proc draw_trim_wiregrid {} {
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set n [xschem get lastsel]
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xschem unselect_all
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## if all wires trimmed correctly we should have 129*128*2 = 33024 segments.
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if {$n == 33024} { puts "Trim wire test: $n segments, OK"} else { puts "Trim wire test FAIL"}
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if {$n == 33024} { puts "Trim wire test: $n segments, OK"} else { puts "Trim wire test FAIL, $n segments"}
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xschem clear force
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}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -22,10 +22,12 @@ v {xschem version=3.4.4 file_version=1.2
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G {}
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K {type=iopin
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format="*.iopin @lab"
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spectre_format="//.iopin @lab"
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template="name=p1 lab=xxx"
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}
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V {}
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S {}
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F {}
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E {}
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L 5 -0 -0 3.125 0 {}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=inout}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -22,10 +22,12 @@ v {xschem version=3.4.4 file_version=1.2
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G {}
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K {type=ipin
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format="*.ipin @lab"
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spectre_format="//.ipin @lab"
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template="name=p1 lab=xxx"
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}
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V {}
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S {}
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F {}
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E {}
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L 5 -5 0 0 0 {}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=out}
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@ -1,4 +1,4 @@
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v {xschem version=3.4.4 file_version=1.2
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v {xschem version=3.4.8RC file_version=1.3
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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@ -22,10 +22,12 @@ v {xschem version=3.4.4 file_version=1.2
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G {}
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K {type=opin
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format="*.opin @lab"
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spectre_format="//.opin @lab"
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template="name=p1 lab=xxx"
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}
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V {}
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S {}
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F {}
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E {}
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L 5 0 0 8.75 0 {}
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B 5 -1.25 -1.25 1.25 1.25 {name=p dir=in}
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