updates to tb_diff_amp.sch (ngspice-verilog-A cosimulation), added couple video links in docs

doc/xschem_man/xschem_man.html

@@ -94,7 +94,8 @@
  <li><a href="https://xschem.sourceforge.io/stefan/xschem_man/video_tutorials/net_name_attribute.mp4">[Video] Let components display the name of the net attached to their pins</a></li>
  <li><a href="https://xschem.sourceforge.io/stefan/xschem_man/video_tutorials/bezier_shapes.mp4">[Video] New editing commands on shapes, polygons and bezier curves.</a></li>
  <li><a href="https://xschem.sourceforge.io/stefan/xschem_man/video_tutorials/click_and_drag.mp4">[Video] New user friendly 'click and drag' interface</a></li>
-
+ <li><a href="https://xschem.sourceforge.io/stefan/xschem_man/video_tutorials/multisim.mp4">[Video] Simulate the same circuit with different simulators, SPICE, Verilog, VHDL</a></li>
+ <li><a href="https://xschem.sourceforge.io/stefan/xschem_man/video_tutorials/verilog_a.mp4">[Video] Ngspice / Verilog-A cosimulation</a></li>
 
 
  </ul>

xschem_library/ngspice/diff_amp.sym

@@ -21,9 +21,9 @@ v {xschem version=3.4.6 file_version=1.2
 }
 G {}
 K {type=opamp_va
-format="@spiceprefix@name @@OUT @@IN1 @@IN2 @model"
+format="@name @@OUT @@IN1 @@IN2 @model"
 
-template="name=U1 model=diff_amp_cell spiceprefix=X"
+template="name=X1 model=diff_amp_cell"
 
 device_model="tcleval(
 .subckt diff_amp_cell OUT IN1 IN2

xschem_library/ngspice/tb_diff_amp.sch

@@ -24,7 +24,7 @@ K {}
 V {}
 S {}
 E {}
-B 2 840 -900 1640 -500 {flags=graph
+B 2 840 -580 1640 -170 {flags=graph
 y1=0
 y2=6
 ypos1=0
@@ -32,43 +32,44 @@ ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=0
-x2=6
+x1=1.1
+x2=1.9
 divx=5
 subdivx=1
 xlabmag=1.0
 ylabmag=1.0
 node="b
-a"
-color="6 4"
+a
+z"
+color="6 4 7"
 dataset=-1
 unitx=1
 logx=0
 logy=0
 }
-B 2 840 -500 1640 -100 {flags=graph
-y1=-30
-y2=30
+B 2 840 -990 1640 -580 {flags=graph
+y1=0
+y2=40
 ypos1=0
 ypos2=2
 divy=5
 subdivy=1
 unity=1
-x1=0
-x2=6
+x1=1.1
+x2=1.9
 divx=5
 subdivx=1
 xlabmag=1.0
 ylabmag=1.0
-node=z
+node="Opamp gain; z deriv()"
 color=7
 dataset=-1
 unitx=1
 logx=0
 logy=0
 }
-P 4 5 140 -620 140 -870 710 -870 710 -620 140 -620 {}
-P 4 7 410 -620 410 -560 420 -560 410 -540 400 -560 410 -560 410 -620 {}
+P 4 5 140 -600 140 -880 710 -880 710 -600 140 -600 {}
+P 4 7 410 -600 410 -560 420 -560 410 -540 400 -560 410 -560 410 -600 {}
 T {// importing libs
 
 `include "discipline.h"
@@ -78,17 +79,19 @@ module diff_amp(
   input electrical in1,
   input electrical in2);
 
-parameter real gain = 10; // setting gain to 10 of the differential amplifier
+parameter real gain = 40; // setting gain to 40 of the differential amplifier
+parameter real vcc = 3;   // swing from -vcc to +vcc
+parameter real offset = 3;// added offset
 
 analog begin
 
-    V(out) <+ gain * (V(in1, in2));
-    // V(out) <+ 2 * atan( gain / 2 * V(in1, in2) );
+    V(out) <+ offset / 2 + vcc / 2 * tanh( gain / vcc * 2 * V(in1, in2));
 
 end
-endmodule} 150 -860 0 0 0.2 0.2 {font=monospace}
+endmodule
+} 150 -870 0 0 0.2 0.2 {font=monospace}
 T {create a diff_amp.va file with following code 
-and compile it into a .osdi file with openvaf.} 190 -930 0 0 0.4 0.4 {}
+and compile it into a .osdi file with openvaf.} 190 -940 0 0 0.4 0.4 {}
 N 180 -450 320 -450 {lab=B}
 N 80 -530 320 -530 {lab=A}
 N 520 -490 640 -490 {lab=Z}
@@ -97,12 +100,12 @@ N 180 -330 180 -290 {lab=0}
 N 80 -330 80 -290 {lab=0}
 N 80 -530 80 -390 {lab=A}
 N 180 -450 180 -390 {lab=B}
-C {diff_amp.sym} 420 -490 0 0 {name=U1}
+C {diff_amp.sym} 420 -490 0 0 {name=X1}
 C {lab_pin.sym} 640 -490 0 1 {name=p1 sig_type=std_logic lab=Z}
 C {lab_pin.sym} 80 -530 0 0 {name=p2 sig_type=std_logic lab=A}
 C {lab_pin.sym} 180 -450 0 0 {name=p3 sig_type=std_logic lab=B}
-C {vsource.sym} 80 -360 0 0 {name=V1 value=3.1 savecurrent=false}
-C {vsource.sym} 180 -360 0 0 {name=V2 value=3 savecurrent=false}
+C {vsource.sym} 80 -360 0 0 {name=V1 value=1.51 savecurrent=false}
+C {vsource.sym} 180 -360 0 0 {name=V2 value=1.5 savecurrent=false}
 C {lab_pin.sym} 60 -290 0 0 {name=p4 sig_type=std_logic lab=0}
 C {code_shown.sym} 240 -320 0 0 {name=COMMANDS only_toplevel=false value="
 .options savecurrents
@@ -111,7 +114,7 @@ C {code_shown.sym} 240 -320 0 0 {name=COMMANDS only_toplevel=false value="
   op
   remzerovec
   write tb_diff_amp.raw
-  dc V1 0 6 0.01
+  dc V1 1.1 1.9 0.001
   set appendwrite
   remzerovec
   write tb_diff_amp.raw