add exit code to xschem netlist command, add execute(error,last) and execute(exitcode,last) to inspect stderr and exit code of last simulation job
This commit is contained in:
stefan schippers
parent
757fd0a378
commit
2725e0c533
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@ -1075,7 +1075,9 @@ C {verilog_timescale.sym} 1050 -100 0 0 {name=s1 timestep="1ns" precision="1ns"
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<li><kbd> toggle_colorscheme</kbd></li><pre>
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Toggle dark/light colorscheme </pre>
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<li><kbd> translate n str</kbd></li><pre>
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Translate string 'str' replacing @xxx tokens with values in instance 'n' attributes </pre>
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Translate string 'str' replacing @xxx tokens with values in instance 'n' attributes
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Example: xschem translate vref {the voltage is @value}
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the voltage is 1.8</pre>
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<li><kbd> trim_wires</kbd></li><pre>
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Remove operlapping wires, join lines, trim wires at intersections </pre>
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<li><kbd> undo</kbd></li><pre>
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161
src/netlist.c
161
src/netlist.c
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@ -241,11 +241,11 @@ void get_square(double x, double y, int *xx, int *yy)
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/* what:
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* 0, XINSERT : add to hash
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* 1, XDELETE : remove from hash
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*/
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static void hash_inst_pin(int what, int i, int j)
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/* inst pin */
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*
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* inst pin */
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static int hash_inst_pin(int what, int i, int j)
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{
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int err = 0;
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xRect *rct;
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char *prop_ptr;
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double x0, y0, rx1, ry1;
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@ -276,6 +276,7 @@ static void hash_inst_pin(int what, int i, int j)
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my_snprintf(str, S(str), "symbol %s: missing all or name or dir attributes on pin %d\n %s",
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xctx->inst[i].name, j, prop_ptr);
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statusmsg(str,2);
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err |= 1;
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tcleval("show_infotext"); /* critical error: force ERC window showing */
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if(!xctx->netlist_count) {
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xctx->inst[i].color = -PINLAYER;
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@ -290,6 +291,7 @@ static void hash_inst_pin(int what, int i, int j)
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get_square(x0, y0, &sqx, &sqy);
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if( what == XINSERT ) instpininsert(i, j, x0, y0, sqx, sqy);
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else instpindelete(i, j, sqx, sqy);
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return err;
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}
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/* what:
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@ -582,7 +584,7 @@ static void name_generics()
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int const instances = xctx->instances;
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/* name generic pins from attached labels */
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dbg(2, "prepare_netlist_structs(): naming generics from attached labels\n");
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dbg(2, "name_generics(): naming generics from attached labels\n");
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if(for_netlist) for (i=0;i<instances; ++i) { /* ... assign node fields on all (non label) instances */
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if(inst[i].ptr<0) continue;
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my_strdup(_ALLOC_ID_, &type,(inst[i].ptr+ xctx->sym)->type);
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@ -608,7 +610,7 @@ static void name_generics()
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if((iptr->x0==x0) && (iptr->y0==y0)) {
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if((inst[n].ptr+ xctx->sym)->type && inst[n].node[p] != NULL &&
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!strcmp((inst[n].ptr+ xctx->sym)->type, "label")) {
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dbg(2, "prepare_netlist_structs(): naming generic %s\n", inst[n].node[p]);
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dbg(2, "name_generics(): naming generic %s\n", inst[n].node[p]);
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my_strdup(_ALLOC_ID_, &inst[i].node[j], get_tok_value(inst[n].prop_ptr,"value",0) );
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if(!for_netlist) {
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my_strdup(_ALLOC_ID_, &sig_type,"");
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@ -633,11 +635,13 @@ static void name_generics()
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if(type) my_free(_ALLOC_ID_, &type);
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}
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static void signal_short( const char *tag, const char *n1, const char *n2)
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static int signal_short( const char *tag, const char *n1, const char *n2)
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{
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int err = 0;
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char str[2048];
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if( n1 && n2 && strcmp( n1, n2) )
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{
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err |= 1;
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my_snprintf(str, S(str), "%s shorted: %s - %s", tag, n1, n2);
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dbg(1, "signal_short(): signal_short: shorted: %s - %s", n1, n2);
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statusmsg(str,2);
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@ -649,6 +653,7 @@ static void signal_short( const char *tag, const char *n1, const char *n2)
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if(tclgetboolvar("incr_hilight")) incr_hilight_color();
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}
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}
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return err;
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}
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static void set_inst_node(int i, int j, const char *node)
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@ -673,10 +678,11 @@ static void set_inst_node(int i, int j, const char *node)
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}
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}
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static void instcheck(int n, int p);
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static int instcheck(int n, int p);
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static void name_attached_inst_to_net(int k, int sqx, int sqy)
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{
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static int name_attached_inst_to_net(int k, int sqx, int sqy)
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{
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int err = 0;
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xInstance * const inst = xctx->inst;
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xWire * const wire = xctx->wire;
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Instpinentry *iptr;
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@ -693,16 +699,18 @@ static void name_attached_inst_to_net(int k, int sqx, int sqy)
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dbg(1, "name_attached_inst_to_net(): inst %s, pin %d <-- %s\n",
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inst[n].instname, p, wire[k].node);
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set_inst_node(n, p, wire[k].node);
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instcheck(n, p);
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err |= instcheck(n, p);
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} else {
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if(for_netlist>0) signal_short("net to named instance pin", wire[k].node, inst[n].node[p]);
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if(for_netlist>0) err |= signal_short("net to named instance pin", wire[k].node, inst[n].node[p]);
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}
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}
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}
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}
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return err;
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}
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static void wirecheck(int k) /* recursive routine */
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static int wirecheck(int k) /* recursive routine */
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{
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int err = 0;
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int tmpi, tmpj, counti, countj, i, j, touches, x1a, x2a, y1a, y2a;
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double x1, y1, x2, y2;
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Wireentry *wptr;
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@ -731,7 +739,7 @@ static void wirecheck(int k) /* recursive routine */
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for(wptr = xctx->wire_spatial_table[tmpi][tmpj]; wptr; wptr = wptr->next) {
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int n = wptr->n;
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if(n == k) { /* itself */
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name_attached_inst_to_net(k, tmpi, tmpj);
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err |= name_attached_inst_to_net(k, tmpi, tmpj);
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continue;
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}
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touches =
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@ -743,19 +751,21 @@ static void wirecheck(int k) /* recursive routine */
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if(!wire[n].node) {
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my_strdup(_ALLOC_ID_, &wire[n].node, wire[k].node);
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my_strdup(_ALLOC_ID_, &wire[n].prop_ptr, subst_token(wire[n].prop_ptr, "lab", wire[n].node));
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name_attached_inst_to_net(n, tmpi, tmpj);
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wirecheck(n); /* recursive check */
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err |= name_attached_inst_to_net(n, tmpi, tmpj);
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err |= wirecheck(n); /* recursive check */
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} else {
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if(for_netlist>0) signal_short("Net to net", wire[n].node, wire[k].node);
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if(for_netlist>0) err |= signal_short("Net to net", wire[n].node, wire[k].node);
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}
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}
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}
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}
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}
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return err;
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}
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static void name_attached_nets(double x0, double y0, int sqx, int sqy, const char *node)
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static int name_attached_nets(double x0, double y0, int sqx, int sqy, const char *node)
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{
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int err = 0;
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xWire * const wire = xctx->wire;
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Wireentry *wptr;
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for(wptr = xctx->wire_spatial_table[sqx][sqy]; wptr; wptr = wptr->next) {
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@ -764,17 +774,18 @@ static void name_attached_nets(double x0, double y0, int sqx, int sqy, const cha
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if(!wire[n].node) {
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my_strdup(_ALLOC_ID_, &wire[n].node, node);
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my_strdup(_ALLOC_ID_, &wire[n].prop_ptr, subst_token(wire[n].prop_ptr, "lab", wire[n].node));
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wirecheck(n);
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err |= wirecheck(n);
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} else {
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if(for_netlist>0) signal_short("Net", wire[n].node, node);
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if(for_netlist>0) err |= signal_short("Net", wire[n].node, node);
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}
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}
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}
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return err;
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}
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static void name_attached_inst(int i, double x0, double y0, int sqx, int sqy, const char *node)
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{
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static int name_attached_inst(int i, double x0, double y0, int sqx, int sqy, const char *node)
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{
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int err = 0;
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xInstance * const inst = xctx->inst;
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Instpinentry *iptr;
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for(iptr = xctx->instpin_spatial_table[sqx][sqy]; iptr; iptr = iptr->next) {
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@ -787,13 +798,13 @@ static void name_attached_inst(int i, double x0, double y0, int sqx, int sqy, co
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if(iptr->x0 == x0 && iptr->y0 == y0 ) {
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if(!inst[n].node[p]) {
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set_inst_node(n, p, node);
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instcheck(n, p);
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err |= instcheck(n, p);
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} else {
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if(for_netlist>0) signal_short("Instance pin", inst[n].node[p], node);
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if(for_netlist>0) err |= signal_short("Instance pin", inst[n].node[p], node);
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}
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}
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}
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return err;
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}
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/* what:
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@ -844,8 +855,9 @@ static int find_pass_through_symbols(int what, int ninst)
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* Given an instance pin (inst n, pin p) propagate electrical information through
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* other pins with identical "name" attribute (pass-through symbols)
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*/
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static void instcheck(int n, int p)
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static int instcheck(int n, int p)
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{
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int err = 0;
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xInstance * const inst = xctx->inst;
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int j, sqx, sqy;
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double x0, y0;
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@ -856,7 +868,7 @@ static void instcheck(int n, int p)
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int rects = xctx->sym[k].rects[PINLAYER];
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char *pin_name = NULL;
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my_strdup(_ALLOC_ID_, &pin_name, get_tok_value(xctx->sym[k].rect[PINLAYER][p].prop_ptr, "name", 0));
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if(p >= rects) return;
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if(p >= rects) return 1;
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for(j = 0; j < rects; ++j) {
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const char *other_pin;
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if(j == p) continue;
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@ -868,22 +880,24 @@ static void instcheck(int n, int p)
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set_inst_node(n, j, inst[n].node[p]);
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get_inst_pin_coord(n, j, &x0, &y0);
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get_square(x0, y0, &sqx, &sqy);
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name_attached_nets(x0, y0, sqx, sqy, inst[n].node[j]);
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name_attached_inst(n, x0, y0, sqx, sqy, inst[n].node[j]);
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err |= name_attached_nets(x0, y0, sqx, sqy, inst[n].node[j]);
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err |= name_attached_inst(n, x0, y0, sqx, sqy, inst[n].node[j]);
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} else {
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if(for_netlist>0) signal_short("Pass_through symbol", inst[n].node[p], inst[n].node[j]);
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if(for_netlist>0) err |= signal_short("Pass_through symbol", inst[n].node[p], inst[n].node[j]);
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}
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}
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}
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my_free(_ALLOC_ID_, &pin_name);
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}
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return err;
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}
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/* starting from labels, ipins, opins, iopins propagate electrical
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* nodes to attached nets and instances
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*/
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static void name_nodes_of_pins_labels_and_propagate()
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static int name_nodes_of_pins_labels_and_propagate()
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{
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int err = 0;
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int i, sqx, sqy;
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double x0, y0;
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int port;
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@ -900,7 +914,7 @@ static void name_nodes_of_pins_labels_and_propagate()
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static int startlevel = 0; /* safe to keep even with multiple schematic windows, netlist is not interruptable */
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if(xctx->netlist_count == 0 ) startlevel = xctx->currsch;
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dbg(2, "prepare_netlist_structs(): naming pins from attrs\n");
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dbg(2, "name_nodes_of_pins_labels_and_propagate(): naming pins from attrs\n");
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/* print_erc is 1 the first time prepare_netlist_structs() is called on top level while
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* doing the netlist, when netlist of sub blocks is completed and toplevel is reloaded
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* a second prepare_netlist_structs() is called to name unnamed nets, in this second call
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@ -955,7 +969,8 @@ static void name_nodes_of_pins_labels_and_propagate()
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port=1;
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/* 20071204 only define a dir property if instance is not a label */
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if(for_netlist)
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my_strdup2(_ALLOC_ID_, &dir, get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][0].prop_ptr, "dir",0));
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my_strdup2(_ALLOC_ID_, &dir,
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get_tok_value( (inst[i].ptr+ xctx->sym)->rect[PINLAYER][0].prop_ptr, "dir",0));
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}
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else {
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/* handle global nodes (global=1 set as symbol property) 28032003 */
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@ -972,11 +987,12 @@ static void name_nodes_of_pins_labels_and_propagate()
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my_strdup(_ALLOC_ID_, &inst[i].node[0], inst[i].lab);
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if(!(inst[i].node[0])) {
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my_strdup(_ALLOC_ID_, &inst[i].node[0], get_tok_value((inst[i].ptr+ xctx->sym)->templ, "lab",0));
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dbg(1, "prepare_netlist_structs(): no lab attr on instance, pick from symbol: %s\n", inst[i].node[0]);
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dbg(1, "name_nodes_of_pins_labels_and_propagate(): no lab attr on instance, pick from symbol: %s\n",
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inst[i].node[0]);
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}
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/* handle global nodes (global=1 set as symbol property) 28032003 */
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if(!strcmp(type,"label") && global_node && !strcmp(global_node, "true")) {
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dbg(1, "prepare_netlist_structs(): global node: %s\n",inst[i].node[0]);
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dbg(1, "name_nodes_of_pins_labels_and_propagate(): global node: %s\n",inst[i].node[0]);
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record_global_node(1,NULL, inst[i].node[0]);
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}
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@ -987,9 +1003,9 @@ static void name_nodes_of_pins_labels_and_propagate()
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get_inst_pin_coord(i, 0, &x0, &y0);
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get_square(x0, y0, &sqx, &sqy);
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/* name nets that touch ioin opin alias instances */
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name_attached_nets(x0, y0, sqx, sqy, inst[i].node[0]);
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err |= name_attached_nets(x0, y0, sqx, sqy, inst[i].node[0]);
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/* name instances that touch ioin opin alias instances */
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name_attached_inst(i, x0, y0, sqx, sqy, inst[i].node[0]);
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err |= name_attached_inst(i, x0, y0, sqx, sqy, inst[i].node[0]);
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} /* if(type && ... */
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} /* for(i=0;i<instances... */
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my_free(_ALLOC_ID_, &dir);
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@ -1001,36 +1017,41 @@ static void name_nodes_of_pins_labels_and_propagate()
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my_free(_ALLOC_ID_, &value);
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my_free(_ALLOC_ID_, &class);
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}
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return err;
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}
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static void set_unnamed_net(int i)
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static int set_unnamed_net(int i)
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{
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int err = 0;
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char tmp_str[30];
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my_snprintf(tmp_str, S(tmp_str), "#net%d", get_unnamed_node(1,0,0));
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my_strdup(_ALLOC_ID_, &xctx->wire[i].node, tmp_str);
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my_strdup(_ALLOC_ID_, &xctx->wire[i].prop_ptr, subst_token(xctx->wire[i].prop_ptr, "lab", tmp_str));
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/* insert unnamed wire name in hash table */
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bus_node_hash_lookup(tmp_str, "", XINSERT, 0,"","","","");
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wirecheck(i);
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err |= wirecheck(i);
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return err;
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}
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static void name_unlabeled_nets()
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static int name_unlabeled_nets()
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{
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int err = 0;
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int i;
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/* name nets that do not touch ipin opin alias instances */
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dbg(2, "prepare_netlist_structs(): naming nets that dont touch labels\n");
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dbg(2, "name_unlabeled_nets(): naming nets that dont touch labels\n");
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for (i = 0; i < xctx->wires; ++i)
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{
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if(xctx->wire[i].node == NULL)
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{
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set_unnamed_net(i);
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err |= set_unnamed_net(i);
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}
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}
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return err;
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}
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static void set_unnamed_inst(int i, int j)
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static int set_unnamed_inst(int i, int j)
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{
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int err = 0;
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char tmp_str[30];
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xInstance * const inst = xctx->inst;
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int sqx, sqy;
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@ -1040,18 +1061,20 @@ static void set_unnamed_inst(int i, int j)
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set_inst_node(i, j, tmp_str);
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get_inst_pin_coord(i, j, &x0, &y0);
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get_square(x0, y0, &sqx, &sqy);
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name_attached_inst(i, x0, y0, sqx, sqy, inst[i].node[j]);
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err |= name_attached_inst(i, x0, y0, sqx, sqy, inst[i].node[j]);
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return err;
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}
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static void name_unlabeled_instances()
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static int name_unlabeled_instances()
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{
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int err = 0;
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int i, j;
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xInstance * const inst = xctx->inst;
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int const instances = xctx->instances;
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int rects;
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/* name nets that do not touch ipin opin alias instances */
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dbg(2, "prepare_netlist_structs(): naming nets that dont touch labels\n");
|
||||
dbg(2, "name_unlabeled_instances(): naming nets that dont touch labels\n");
|
||||
for (i = 0; i < instances; ++i)
|
||||
{
|
||||
if(inst[i].ptr != -1) {
|
||||
|
|
@ -1059,22 +1082,23 @@ static void name_unlabeled_instances()
|
|||
for(j = 0; j < rects; ++j) {
|
||||
if(inst[i].node[j] == NULL)
|
||||
{
|
||||
set_unnamed_inst(i, j);
|
||||
err |= set_unnamed_inst(i, j);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
static void reset_node_data_and_rehash()
|
||||
static int reset_node_data_and_rehash()
|
||||
{
|
||||
int err = 0;
|
||||
int i,j, rects;
|
||||
xInstance * const inst = xctx->inst;
|
||||
int const instances = xctx->instances;
|
||||
|
||||
/* reset wire & inst node labels */
|
||||
dbg(2, "prepare_netlist_structs(): rehashing wires and instance pins in spatial hash table\n");
|
||||
dbg(2, "reset_node_data_and_rehash(): rehashing wires and instance pins in spatial hash table\n");
|
||||
hash_wires();
|
||||
for (i=0;i<instances; ++i)
|
||||
{
|
||||
|
|
@ -1087,19 +1111,20 @@ static void reset_node_data_and_rehash()
|
|||
for (j=0;j<rects; ++j)
|
||||
{
|
||||
inst[i].node[j]=NULL;
|
||||
hash_inst_pin(XINSERT, i, j);
|
||||
err |= hash_inst_pin(XINSERT, i, j);
|
||||
}
|
||||
}
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
void prepare_netlist_structs(int for_netl)
|
||||
int prepare_netlist_structs(int for_netl)
|
||||
{
|
||||
int err = 0;
|
||||
char nn[PATH_MAX+30];
|
||||
|
||||
for_netlist = for_netl;
|
||||
if(for_netlist>0 && xctx->prep_net_structs) return;
|
||||
else if(!for_netlist && xctx->prep_hi_structs) return;
|
||||
if(for_netlist>0 && xctx->prep_net_structs) return 0;
|
||||
else if(!for_netlist && xctx->prep_hi_structs) return 0;
|
||||
/* delete instance pins spatial hash, wires spatial hash, node_hash, wires and inst nodes.*/
|
||||
if(for_netlist) {
|
||||
my_snprintf(nn, S(nn), "-----------%s", xctx->sch[xctx->currsch]);
|
||||
|
|
@ -1108,12 +1133,12 @@ void prepare_netlist_structs(int for_netl)
|
|||
dbg(1, "prepare_netlist_structs(): extraction: %s\n", xctx->sch[xctx->currsch]);
|
||||
delete_netlist_structs();
|
||||
free_simdata(); /* invalidate simulation cache */
|
||||
reset_node_data_and_rehash();
|
||||
err |= reset_node_data_and_rehash();
|
||||
get_unnamed_node(0,0,0); /*initializes node multiplicity data struct */
|
||||
find_pass_through_symbols(0, 0); /* initialize data struct to quickly find pass-through syms */
|
||||
name_nodes_of_pins_labels_and_propagate();
|
||||
name_unlabeled_nets();
|
||||
name_unlabeled_instances();
|
||||
err |= name_nodes_of_pins_labels_and_propagate();
|
||||
err |= name_unlabeled_nets();
|
||||
err |= name_unlabeled_instances();
|
||||
name_generics();
|
||||
/* name_non_label_inst_pins(); */
|
||||
|
||||
|
|
@ -1126,6 +1151,7 @@ void prepare_netlist_structs(int for_netl)
|
|||
dbg(1, "prepare_netlist_structs(): returning\n");
|
||||
/* avoid below call: it in turn calls prepare_netlist_structs(), too many side effects */
|
||||
/* propagate_hilights(1, 0, XINSERT_NOREPLACE);*/
|
||||
return err;
|
||||
}
|
||||
|
||||
void delete_inst_node(int i)
|
||||
|
|
@ -1165,6 +1191,7 @@ void delete_netlist_structs(void)
|
|||
|
||||
int warning_overlapped_symbols(int sel)
|
||||
{
|
||||
int err = 0;
|
||||
int i;
|
||||
Int_hashtable table = {NULL, 0};
|
||||
Int_hashentry *found;
|
||||
|
|
@ -1191,16 +1218,18 @@ int warning_overlapped_symbols(int sel)
|
|||
my_snprintf(str, S(str), "Warning: overlapped instance found: %s(%s) -> %s\n",
|
||||
xctx->inst[i].instname, xctx->inst[i].name, xctx->inst[found->value].instname);
|
||||
statusmsg(str,2);
|
||||
err |= 1;
|
||||
tcleval("show_infotext"); /* critical error: force ERC window showing */
|
||||
}
|
||||
}
|
||||
int_hash_free(&table);
|
||||
if(sel && xctx->need_reb_sel_arr) rebuild_selected_array();
|
||||
return 0;
|
||||
return err;
|
||||
}
|
||||
|
||||
int sym_vs_sch_pins()
|
||||
{
|
||||
int err = 0;
|
||||
char **lab_array =NULL;
|
||||
int lab_array_size = 0;
|
||||
int i, j, k, symbol, n_syms, rects, pin_cnt=0, pin_match, mult;
|
||||
|
|
@ -1348,6 +1377,7 @@ int sym_vs_sch_pins()
|
|||
statusmsg(str,2);
|
||||
my_snprintf(str, S(str), " %s <--> %s", type, pin_dir);
|
||||
statusmsg(str,2);
|
||||
err |= 1;
|
||||
tcleval("show_infotext"); /* critical error: force ERC window showing */
|
||||
for(j = 0; j < xctx->instances; ++j) {
|
||||
if(!xctx->x_strcmp(xctx->inst[j].name, xctx->sym[i].name)) {
|
||||
|
|
@ -1365,6 +1395,7 @@ int sym_vs_sch_pins()
|
|||
/* fprintf(errfp, " unmatched sch / sym pin: %s\n", lab); */
|
||||
my_snprintf(str, S(str), "Symbol %s: schematic pin: %s not in symbol", xctx->sym[i].name, lab);
|
||||
statusmsg(str,2);
|
||||
err |= 1;
|
||||
tcleval("show_infotext"); /* critical error: force ERC window showing */
|
||||
for(j = 0; j < xctx->instances; ++j) {
|
||||
if(!xctx->x_strcmp(xctx->inst[j].name, xctx->sym[i].name)) {
|
||||
|
|
@ -1399,6 +1430,7 @@ int sym_vs_sch_pins()
|
|||
my_snprintf(str, S(str), "Symbol %s has %d pins, its schematic has %d pins",
|
||||
xctx->sym[i].name, rects, pin_cnt);
|
||||
statusmsg(str,2);
|
||||
err |= 1;
|
||||
tcleval("show_infotext"); /* critical error: force ERC window showing */
|
||||
for(j = 0; j < xctx->instances; ++j) {
|
||||
if(!xctx->x_strcmp(xctx->inst[j].name, xctx->sym[i].name)) {
|
||||
|
|
@ -1423,6 +1455,7 @@ int sym_vs_sch_pins()
|
|||
my_snprintf(str, S(str), "Symbol %s: symbol pin: %s not in schematic",
|
||||
xctx->sym[i].name, pin_name ? pin_name : "<NULL>");
|
||||
statusmsg(str,2);
|
||||
err |= 1;
|
||||
tcleval("show_infotext"); /* critical error: force ERC window showing */
|
||||
for(k = 0; k < xctx->instances; ++k) {
|
||||
if(!xctx->x_strcmp(xctx->inst[k].name, xctx->sym[i].name)) {
|
||||
|
|
@ -1450,5 +1483,5 @@ int sym_vs_sch_pins()
|
|||
} /* for(i=0;i<n_syms; ++i) */
|
||||
|
||||
while(xctx->symbols > n_syms) remove_symbol(xctx->symbols - 1);
|
||||
return 0;
|
||||
return err;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -192,9 +192,10 @@ void node_hash_free(void) /* remove the whole hash table */
|
|||
}
|
||||
}
|
||||
|
||||
void traverse_node_hash()
|
||||
int traverse_node_hash()
|
||||
{
|
||||
int i;
|
||||
int err = 0;
|
||||
Node_hashentry *entry;
|
||||
char str[2048]; /* 20161122 overflow safe */
|
||||
int incr_hi;
|
||||
|
|
@ -211,7 +212,8 @@ void traverse_node_hash()
|
|||
my_snprintf(str, S(str), "undriven node: %s", entry->token);
|
||||
if(!xctx->netlist_count) bus_hilight_hash_lookup(entry->token, xctx->hilight_color, XINSERT_NOREPLACE);
|
||||
if(incr_hi) incr_hilight_color();
|
||||
statusmsg(str,2);
|
||||
statusmsg(str, 2);
|
||||
err |= 1;
|
||||
tcleval("show_infotext"); /* critical error: force ERC window showing */
|
||||
}
|
||||
else if(entry->d.out + entry->d.inout + entry->d.in == 1)
|
||||
|
|
@ -249,6 +251,7 @@ void traverse_node_hash()
|
|||
entry = entry->next;
|
||||
}
|
||||
}
|
||||
return err;
|
||||
}
|
||||
|
||||
void print_vhdl_signals(FILE *fd)
|
||||
|
|
|
|||
|
|
@ -2045,20 +2045,21 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
|
|||
* do a netlist of current schematic in currently defined netlist format */
|
||||
else if(!strcmp(argv[1], "netlist") )
|
||||
{
|
||||
int err = 0;
|
||||
yyparse_error = 0;
|
||||
if(set_netlist_dir(0, NULL) ) {
|
||||
if(xctx->netlist_type == CAD_SPICE_NETLIST)
|
||||
global_spice_netlist(1); /* 1 means global netlist */
|
||||
err = global_spice_netlist(1); /* 1 means global netlist */
|
||||
else if(xctx->netlist_type == CAD_VHDL_NETLIST)
|
||||
global_vhdl_netlist(1);
|
||||
err = global_vhdl_netlist(1);
|
||||
else if(xctx->netlist_type == CAD_VERILOG_NETLIST)
|
||||
global_verilog_netlist(1);
|
||||
err = global_verilog_netlist(1);
|
||||
else if(xctx->netlist_type == CAD_TEDAX_NETLIST)
|
||||
global_tedax_netlist(1);
|
||||
else
|
||||
if(has_x) tcleval("tk_messageBox -type ok -parent [xschem get topwindow] "
|
||||
"-message {Please Set netlisting mode (Options menu)}");
|
||||
Tcl_ResetResult(interp);
|
||||
Tcl_SetResult(interp, my_itoa(err), TCL_VOLATILE);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -2566,12 +2567,13 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
|
|||
Rebuild logical connectivity abstraction of schematic */
|
||||
else if(!strcmp(argv[1], "rebuild_connectivity"))
|
||||
{
|
||||
int err = 0;
|
||||
xctx->prep_hash_inst=0;
|
||||
xctx->prep_hash_wires=0;
|
||||
xctx->prep_net_structs=0;
|
||||
xctx->prep_hi_structs=0;
|
||||
prepare_netlist_structs(1);
|
||||
Tcl_ResetResult(interp);
|
||||
err |= prepare_netlist_structs(1);
|
||||
Tcl_SetResult(interp, my_itoa(err), TCL_VOLATILE);
|
||||
}
|
||||
|
||||
/* rebuild_selection
|
||||
|
|
@ -3441,12 +3443,20 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
|
|||
}
|
||||
|
||||
/* translate n str
|
||||
* Translate string 'str' replacing @xxx tokens with values in instance 'n' attributes */
|
||||
* Translate string 'str' replacing @xxx tokens with values in instance 'n' attributes
|
||||
* Example: xschem translate vref {the voltage is @value}
|
||||
* the voltage is 1.8 */
|
||||
|
||||
else if(!strcmp(argv[1], "translate") )
|
||||
{
|
||||
if(argc>3) {
|
||||
int i;
|
||||
char *s = NULL;
|
||||
my_strdup2(_ALLOC_ID_, &s, translate(atoi(argv[2]), argv[3]));
|
||||
if((i = get_instance(argv[2])) < 0 ) {
|
||||
Tcl_SetResult(interp, "xschem translate: instance not found", TCL_STATIC);
|
||||
return TCL_ERROR;
|
||||
}
|
||||
my_strdup2(_ALLOC_ID_, &s, translate(i, argv[3]));
|
||||
Tcl_ResetResult(interp);
|
||||
Tcl_SetResult(interp, s, TCL_VOLATILE);
|
||||
my_free(_ALLOC_ID_, &s);
|
||||
|
|
|
|||
|
|
@ -137,8 +137,9 @@ static char *model_name(const char *m)
|
|||
return model_name_result;
|
||||
}
|
||||
|
||||
static void spice_netlist(FILE *fd, int spice_stop )
|
||||
static int spice_netlist(FILE *fd, int spice_stop )
|
||||
{
|
||||
int err = 0;
|
||||
int i, flag = 0;
|
||||
char *type=NULL;
|
||||
int top_sub;
|
||||
|
|
@ -147,8 +148,8 @@ static void spice_netlist(FILE *fd, int spice_stop )
|
|||
if(!spice_stop) {
|
||||
dbg(1, "spice_netlist(): invoke prepare_netlist_structs for %s\n", xctx->current_name);
|
||||
xctx->prep_net_structs = 0;
|
||||
prepare_netlist_structs(1);
|
||||
traverse_node_hash(); /* print all warnings about unconnected floatings etc */
|
||||
err |= prepare_netlist_structs(1);
|
||||
err |= traverse_node_hash(); /* print all warnings about unconnected floatings etc */
|
||||
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
|
||||
{
|
||||
if( strcmp(get_tok_value(xctx->inst[i].prop_ptr,"spice_ignore",0),"true")==0 ) continue;
|
||||
|
|
@ -209,10 +210,12 @@ static void spice_netlist(FILE *fd, int spice_stop )
|
|||
my_free(_ALLOC_ID_, &type);
|
||||
}
|
||||
if(!spice_stop && !xctx->netlist_count) redraw_hilights(0); /* draw_hilight_net(1); */
|
||||
return err;
|
||||
}
|
||||
|
||||
void global_spice_netlist(int global) /* netlister driver */
|
||||
int global_spice_netlist(int global) /* netlister driver */
|
||||
{
|
||||
int err = 0;
|
||||
int first;
|
||||
FILE *fd;
|
||||
const char *str_tmp;
|
||||
|
|
@ -255,7 +258,7 @@ void global_spice_netlist(int global) /* netlister driver */
|
|||
fd=fopen(netl_filename, "w");
|
||||
if(fd==NULL) {
|
||||
dbg(0, "global_spice_netlist(): problems opening netlist file\n");
|
||||
return;
|
||||
return 1;
|
||||
}
|
||||
fprintf(fd, "** sch_path: %s\n", xctx->sch[xctx->currsch]);
|
||||
|
||||
|
|
@ -320,7 +323,7 @@ void global_spice_netlist(int global) /* netlister driver */
|
|||
}
|
||||
fprintf(fd,"\n");
|
||||
|
||||
spice_netlist(fd, 0);
|
||||
err |= spice_netlist(fd, 0);
|
||||
|
||||
first = 0;
|
||||
for(i=0;i<xctx->instances; ++i) /* print netlist_commands of top level cell with no 'place=end' property
|
||||
|
|
@ -374,7 +377,7 @@ void global_spice_netlist(int global) /* netlister driver */
|
|||
}
|
||||
|
||||
/* warning if two symbols perfectly overlapped */
|
||||
warning_overlapped_symbols(0);
|
||||
err |= warning_overlapped_symbols(0);
|
||||
/* preserve current level instance flags before descending hierarchy for netlisting, restore later */
|
||||
stored_flags = my_calloc(_ALLOC_ID_, xctx->instances, sizeof(unsigned int));
|
||||
for(i=0;i<xctx->instances; ++i) stored_flags[i] = xctx->inst[i].color;
|
||||
|
|
@ -408,12 +411,12 @@ void global_spice_netlist(int global) /* netlister driver */
|
|||
{
|
||||
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
|
||||
if( split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_netlist",0),"true")==0 )
|
||||
vhdl_block_netlist(fd, i);
|
||||
err |= vhdl_block_netlist(fd, i);
|
||||
else if(split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_netlist",0),"true")==0 )
|
||||
verilog_block_netlist(fd, i);
|
||||
err |= verilog_block_netlist(fd, i);
|
||||
else
|
||||
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_primitive",0),"true") )
|
||||
spice_block_netlist(fd, i);
|
||||
err |= spice_block_netlist(fd, i);
|
||||
}
|
||||
}
|
||||
my_free(_ALLOC_ID_, &abs_path);
|
||||
|
|
@ -428,9 +431,9 @@ void global_spice_netlist(int global) /* netlister driver */
|
|||
xctx->pop_undo(0, 0);
|
||||
my_strncpy(xctx->current_name, rel_sym_path(xctx->sch[xctx->currsch]), S(xctx->current_name));
|
||||
dbg(1, "spice_netlist(): invoke prepare_netlist_structs for %s\n", xctx->current_name);
|
||||
prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
|
||||
err |= prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
|
||||
/* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
|
||||
sym_vs_sch_pins();
|
||||
err |= sym_vs_sch_pins();
|
||||
if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
|
||||
}
|
||||
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
|
||||
|
|
@ -506,10 +509,12 @@ void global_spice_netlist(int global) /* netlister driver */
|
|||
my_free(_ALLOC_ID_, &type);
|
||||
my_free(_ALLOC_ID_, &place);
|
||||
xctx->netlist_count = 0;
|
||||
return err;
|
||||
}
|
||||
|
||||
void spice_block_netlist(FILE *fd, int i)
|
||||
int spice_block_netlist(FILE *fd, int i)
|
||||
{
|
||||
int err = 0;
|
||||
int spice_stop=0;
|
||||
char netl_filename[PATH_MAX];
|
||||
char tcl_cmd_netlist[PATH_MAX + 100];
|
||||
|
|
@ -560,7 +565,7 @@ void spice_block_netlist(FILE *fd, int i)
|
|||
fprintf(fd, "\n");
|
||||
|
||||
spice_stop ? load_schematic(0,filename, 0) : load_schematic(1,filename, 0);
|
||||
spice_netlist(fd, spice_stop); /* 20111113 added spice_stop */
|
||||
err |= spice_netlist(fd, spice_stop); /* 20111113 added spice_stop */
|
||||
|
||||
if(xctx->schprop && xctx->schprop[0]) {
|
||||
fprintf(fd,"**** begin user architecture code\n");
|
||||
|
|
@ -582,6 +587,7 @@ void spice_block_netlist(FILE *fd, int i)
|
|||
if(debug_var==0) xunlink(netl_filename);
|
||||
}
|
||||
xctx->netlist_count++;
|
||||
return err;
|
||||
}
|
||||
|
||||
/* GENERIC PURPOSE HASH TABLE */
|
||||
|
|
|
|||
|
|
@ -22,15 +22,16 @@
|
|||
|
||||
#include "xschem.h"
|
||||
|
||||
static void tedax_netlist(FILE *fd, int tedax_stop )
|
||||
static int tedax_netlist(FILE *fd, int tedax_stop )
|
||||
{
|
||||
int err = 0;
|
||||
int i;
|
||||
char *type=NULL;
|
||||
|
||||
if(!tedax_stop) {
|
||||
xctx->prep_net_structs = 0;
|
||||
prepare_netlist_structs(1);
|
||||
traverse_node_hash(); /* print all warnings about unconnected floatings etc */
|
||||
err |= prepare_netlist_structs(1);
|
||||
err |= traverse_node_hash(); /* print all warnings about unconnected floatings etc */
|
||||
}
|
||||
if(!tedax_stop) {
|
||||
for(i=0;i<xctx->instances; ++i) /* print first ipin/opin defs ... */
|
||||
|
|
@ -71,10 +72,12 @@ static void tedax_netlist(FILE *fd, int tedax_stop )
|
|||
my_free(_ALLOC_ID_, &type);
|
||||
}
|
||||
if(!tedax_stop && !xctx->netlist_count) redraw_hilights(0); /* draw_hilight_net(1); */
|
||||
return err;
|
||||
}
|
||||
|
||||
static void tedax_block_netlist(FILE *fd, int i)
|
||||
static int tedax_block_netlist(FILE *fd, int i)
|
||||
{
|
||||
int err = 0;
|
||||
int tedax_stop=0;
|
||||
char filename[PATH_MAX];
|
||||
char *extra=NULL;
|
||||
|
|
@ -104,7 +107,7 @@ static void tedax_block_netlist(FILE *fd, int i)
|
|||
my_free(_ALLOC_ID_, &extra);
|
||||
fprintf(fd, "\n");
|
||||
load_schematic(1,filename, 0);
|
||||
tedax_netlist(fd, tedax_stop);
|
||||
err |= tedax_netlist(fd, tedax_stop);
|
||||
xctx->netlist_count++;
|
||||
|
||||
if(xctx->schprop && xctx->schprop[0]) {
|
||||
|
|
@ -113,10 +116,12 @@ static void tedax_block_netlist(FILE *fd, int i)
|
|||
fprintf(fd,"#**** end user architecture code\n");
|
||||
}
|
||||
fprintf(fd, "end netlist\n\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
void global_tedax_netlist(int global) /* netlister driver */
|
||||
int global_tedax_netlist(int global) /* netlister driver */
|
||||
{
|
||||
int err = 0;
|
||||
FILE *fd;
|
||||
const char *str_tmp;
|
||||
int i;
|
||||
|
|
@ -142,7 +147,7 @@ void global_tedax_netlist(int global) /* netlister driver */
|
|||
fd=fopen(netl_filename, "w");
|
||||
if(fd==NULL){
|
||||
dbg(0, "global_tedax_netlist(): problems opening netlist file\n");
|
||||
return;
|
||||
return 1;
|
||||
}
|
||||
fprintf(fd, "## sch_path: %s\n", xctx->sch[xctx->currsch]);
|
||||
|
||||
|
|
@ -174,7 +179,7 @@ void global_tedax_netlist(int global) /* netlister driver */
|
|||
fprintf(fd, "end netlist\n");
|
||||
|
||||
/* warning if two symbols perfectly overlapped */
|
||||
warning_overlapped_symbols(0);
|
||||
err |= warning_overlapped_symbols(0);
|
||||
/* preserve current level instance flags before descending hierarchy for netlisting, restore later */
|
||||
stored_flags = my_calloc(_ALLOC_ID_, xctx->instances, sizeof(unsigned int));
|
||||
for(i=0;i<xctx->instances; ++i) stored_flags[i] = xctx->inst[i].color;
|
||||
|
|
@ -200,7 +205,7 @@ void global_tedax_netlist(int global) /* netlister driver */
|
|||
my_strdup2(_ALLOC_ID_, &abs_path, abs_sym_path(xctx->sym[i].name, ""));
|
||||
if(strcmp(xctx->sym[i].type,"subcircuit")==0 && check_lib(1, abs_path))
|
||||
{
|
||||
tedax_block_netlist(fd, i);
|
||||
err |= tedax_block_netlist(fd, i);
|
||||
}
|
||||
}
|
||||
my_free(_ALLOC_ID_, &abs_path);
|
||||
|
|
@ -210,7 +215,7 @@ void global_tedax_netlist(int global) /* netlister driver */
|
|||
unselect_all(1);
|
||||
xctx->pop_undo(0, 0);
|
||||
my_strncpy(xctx->current_name, rel_sym_path(xctx->sch[xctx->currsch]), S(xctx->current_name));
|
||||
prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
|
||||
err |= prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
|
||||
|
||||
/* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
|
||||
sym_vs_sch_pins();
|
||||
|
|
|
|||
|
|
@ -22,17 +22,16 @@
|
|||
|
||||
#include "xschem.h"
|
||||
|
||||
static void verilog_netlist(FILE *fd , int verilog_stop)
|
||||
static int verilog_netlist(FILE *fd , int verilog_stop)
|
||||
{
|
||||
int err = 0;
|
||||
int i;
|
||||
char *type=NULL;
|
||||
|
||||
if(!verilog_stop) {
|
||||
xctx->prep_net_structs = 0;
|
||||
prepare_netlist_structs(1);
|
||||
dbg(2, "verilog_netlist(): end prepare_netlist_structs\n");
|
||||
traverse_node_hash(); /* print all warnings about unconnected floatings etc */
|
||||
dbg(2, "verilog_netlist(): end traverse_node_hash\n");
|
||||
err |= prepare_netlist_structs(1);
|
||||
err |= traverse_node_hash(); /* print all warnings about unconnected floatings etc */
|
||||
}
|
||||
|
||||
fprintf(fd,"---- begin signal list\n"); /* these are needed even if signal list empty */
|
||||
|
|
@ -70,10 +69,12 @@ static void verilog_netlist(FILE *fd , int verilog_stop)
|
|||
}
|
||||
dbg(1, "verilog_netlist(): end\n");
|
||||
if(!verilog_stop && !xctx->netlist_count) redraw_hilights(0); /*draw_hilight_net(1); */
|
||||
return err;
|
||||
}
|
||||
|
||||
void global_verilog_netlist(int global) /* netlister driver */
|
||||
int global_verilog_netlist(int global) /* netlister driver */
|
||||
{
|
||||
int err = 0;
|
||||
FILE *fd;
|
||||
const char *str_tmp;
|
||||
char *sig_type = NULL;
|
||||
|
|
@ -106,7 +107,7 @@ void global_verilog_netlist(int global) /* netlister driver */
|
|||
fd=fopen(netl_filename, "w");
|
||||
if(fd==NULL){
|
||||
dbg(0, "global_verilog_netlist(): problems opening netlist file\n");
|
||||
return;
|
||||
return 1;
|
||||
}
|
||||
fprintf(fd, "// sch_path: %s\n", xctx->sch[xctx->currsch]);
|
||||
|
||||
|
|
@ -293,7 +294,7 @@ void global_verilog_netlist(int global) /* netlister driver */
|
|||
}
|
||||
|
||||
dbg(1, "global_verilog_netlist(): netlisting top level\n");
|
||||
verilog_netlist(fd, 0);
|
||||
err |= verilog_netlist(fd, 0);
|
||||
xctx->netlist_count++;
|
||||
fprintf(fd,"---- begin user architecture code\n");
|
||||
|
||||
|
|
@ -330,7 +331,7 @@ void global_verilog_netlist(int global) /* netlister driver */
|
|||
}
|
||||
|
||||
/* warning if two symbols perfectly overlapped */
|
||||
warning_overlapped_symbols(0);
|
||||
err |= warning_overlapped_symbols(0);
|
||||
/* preserve current level instance flags before descending hierarchy for netlisting, restore later */
|
||||
stored_flags = my_calloc(_ALLOC_ID_, xctx->instances, sizeof(unsigned int));
|
||||
for(i=0;i<xctx->instances; ++i) stored_flags[i] = xctx->inst[i].color;
|
||||
|
|
@ -362,12 +363,11 @@ void global_verilog_netlist(int global) /* netlister driver */
|
|||
{
|
||||
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
|
||||
if( split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_netlist",0),"true")==0 )
|
||||
vhdl_block_netlist(fd, i);
|
||||
err |= vhdl_block_netlist(fd, i);
|
||||
else if(split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_netlist",0),"true")==0 )
|
||||
spice_block_netlist(fd, i);
|
||||
else
|
||||
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_primitive",0), "true"))
|
||||
verilog_block_netlist(fd, i);
|
||||
err |= spice_block_netlist(fd, i);
|
||||
else if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_primitive",0), "true"))
|
||||
err |= verilog_block_netlist(fd, i);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -379,9 +379,9 @@ void global_verilog_netlist(int global) /* netlister driver */
|
|||
unselect_all(1);
|
||||
xctx->pop_undo(0, 0);
|
||||
my_strncpy(xctx->current_name, rel_sym_path(xctx->sch[xctx->currsch]), S(xctx->current_name));
|
||||
prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
|
||||
err |= prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
|
||||
/* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
|
||||
sym_vs_sch_pins();
|
||||
err |= sym_vs_sch_pins();
|
||||
if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
|
||||
}
|
||||
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
|
||||
|
|
@ -408,11 +408,13 @@ void global_verilog_netlist(int global) /* netlister driver */
|
|||
my_free(_ALLOC_ID_, &tmp_string);
|
||||
my_free(_ALLOC_ID_, &type);
|
||||
xctx->netlist_count = 0;
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
void verilog_block_netlist(FILE *fd, int i)
|
||||
int verilog_block_netlist(FILE *fd, int i)
|
||||
{
|
||||
int err = 0;
|
||||
int j, l, tmp;
|
||||
int verilog_stop=0;
|
||||
char *dir_tmp = NULL;
|
||||
|
|
@ -564,7 +566,7 @@ void verilog_block_netlist(FILE *fd, int i)
|
|||
}
|
||||
}
|
||||
dbg(1, "verilog_block_netlist(): netlisting %s\n", skip_dir( xctx->sch[xctx->currsch]));
|
||||
verilog_netlist(fd, verilog_stop);
|
||||
err |= verilog_netlist(fd, verilog_stop);
|
||||
fprintf(fd,"---- begin user architecture code\n");
|
||||
for(l=0;l<xctx->instances; ++l) {
|
||||
if( strcmp(get_tok_value(xctx->inst[l].prop_ptr,"verilog_ignore",0),"true")==0 ) continue;
|
||||
|
|
@ -607,5 +609,6 @@ void verilog_block_netlist(FILE *fd, int i)
|
|||
if(debug_var==0) xunlink(netl_filename);
|
||||
}
|
||||
xctx->netlist_count++;
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -23,16 +23,17 @@
|
|||
#include "xschem.h"
|
||||
|
||||
|
||||
static void vhdl_netlist(FILE *fd , int vhdl_stop)
|
||||
static int vhdl_netlist(FILE *fd , int vhdl_stop)
|
||||
{
|
||||
int err = 0;
|
||||
int i,l;
|
||||
char *type=NULL;
|
||||
|
||||
/* set_modify(1); */ /* 20160302 prepare_netlist_structs could change schematic (wire node naming for example) */
|
||||
if(!vhdl_stop) {
|
||||
xctx->prep_net_structs = 0;
|
||||
prepare_netlist_structs(1);
|
||||
traverse_node_hash(); /* print all warnings about unconnected floatings etc */
|
||||
err |= prepare_netlist_structs(1);
|
||||
err |= traverse_node_hash(); /* print all warnings about unconnected floatings etc */
|
||||
}
|
||||
|
||||
dbg(1, "vhdl_netlist(): architecture declarations\n");
|
||||
|
|
@ -109,10 +110,12 @@ static void vhdl_netlist(FILE *fd , int vhdl_stop)
|
|||
if(type) my_free(_ALLOC_ID_, &type);
|
||||
dbg(1, "vhdl_netlist(): end\n");
|
||||
if(!vhdl_stop && !xctx->netlist_count) redraw_hilights(0); /* draw_hilight_net(1); */
|
||||
return err;
|
||||
}
|
||||
|
||||
void global_vhdl_netlist(int global) /* netlister driver */
|
||||
int global_vhdl_netlist(int global) /* netlister driver */
|
||||
{
|
||||
int err = 0;
|
||||
FILE *fd;
|
||||
const char *str_tmp;
|
||||
char *dir_tmp = NULL;
|
||||
|
|
@ -145,7 +148,7 @@ void global_vhdl_netlist(int global) /* netlister driver */
|
|||
|
||||
if(fd==NULL){
|
||||
dbg(0, "global_vhdl_netlist(): problems opening netlist file\n");
|
||||
return;
|
||||
return 1;
|
||||
}
|
||||
fprintf(fd, "-- sch_path: %s\n", xctx->sch[xctx->currsch]);
|
||||
|
||||
|
|
@ -389,7 +392,7 @@ void global_vhdl_netlist(int global) /* netlister driver */
|
|||
my_free(_ALLOC_ID_, &subckt_name);
|
||||
|
||||
dbg(1, "global_vhdl_netlist(): netlisting top level\n");
|
||||
vhdl_netlist(fd, 0);
|
||||
err |= vhdl_netlist(fd, 0);
|
||||
fprintf(fd,"//// begin user architecture code\n");
|
||||
|
||||
for(i=0;i<xctx->instances; ++i) {
|
||||
|
|
@ -424,7 +427,7 @@ void global_vhdl_netlist(int global) /* netlister driver */
|
|||
xctx->netlist_count++;
|
||||
|
||||
/* warning if two symbols perfectly overlapped */
|
||||
warning_overlapped_symbols(0);
|
||||
err |= warning_overlapped_symbols(0);
|
||||
/* preserve current level instance flags before descending hierarchy for netlisting, restore later */
|
||||
stored_flags = my_calloc(_ALLOC_ID_, xctx->instances, sizeof(unsigned int));
|
||||
for(i=0;i<xctx->instances; ++i) stored_flags[i] = xctx->inst[i].color;
|
||||
|
|
@ -458,12 +461,11 @@ void global_vhdl_netlist(int global) /* netlister driver */
|
|||
{
|
||||
str_hash_lookup(&subckt_table, subckt_name, "", XINSERT);
|
||||
if( split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"verilog_netlist",0),"true")==0 )
|
||||
verilog_block_netlist(fd, i);
|
||||
err |= verilog_block_netlist(fd, i);
|
||||
else if( split_f && strcmp(get_tok_value(xctx->sym[i].prop_ptr,"spice_netlist",0),"true")==0 )
|
||||
spice_block_netlist(fd, i);
|
||||
else
|
||||
if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_primitive",0),"true"))
|
||||
vhdl_block_netlist(fd, i);
|
||||
err |= spice_block_netlist(fd, i);
|
||||
else if( strcmp(get_tok_value(xctx->sym[i].prop_ptr,"vhdl_primitive",0),"true"))
|
||||
err |= vhdl_block_netlist(fd, i);
|
||||
}
|
||||
}
|
||||
my_free(_ALLOC_ID_, &abs_path);
|
||||
|
|
@ -475,9 +477,9 @@ void global_vhdl_netlist(int global) /* netlister driver */
|
|||
unselect_all(1);
|
||||
xctx->pop_undo(0, 0);
|
||||
my_strncpy(xctx->current_name, rel_sym_path(xctx->sch[xctx->currsch]), S(xctx->current_name));
|
||||
prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
|
||||
err |= prepare_netlist_structs(1); /* so 'lab=...' attributes for unnamed nets are set */
|
||||
/* symbol vs schematic pin check, we do it here since now we have ALL symbols loaded */
|
||||
sym_vs_sch_pins();
|
||||
err |= sym_vs_sch_pins();
|
||||
if(!xctx->hilight_nets) xctx->hilight_nets = saved_hilight_nets;
|
||||
}
|
||||
/* restore hilight flags from errors found analyzing top level before descending hierarchy */
|
||||
|
|
@ -502,11 +504,12 @@ void global_vhdl_netlist(int global) /* netlister driver */
|
|||
my_free(_ALLOC_ID_, &type);
|
||||
my_free(_ALLOC_ID_, &port_value);
|
||||
xctx->netlist_count = 0;
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
void vhdl_block_netlist(FILE *fd, int i)
|
||||
int vhdl_block_netlist(FILE *fd, int i)
|
||||
{
|
||||
int err = 0;
|
||||
int j,k,l, tmp, found;
|
||||
int vhdl_stop=0;
|
||||
char *dir_tmp = NULL;
|
||||
|
|
@ -692,7 +695,7 @@ void vhdl_block_netlist(FILE *fd, int i)
|
|||
} /* if(!vhdl_stop) */
|
||||
my_free(_ALLOC_ID_, &abs_path);
|
||||
dbg(1, "vhdl_block_netlist(): netlisting %s\n", skip_dir( xctx->sch[xctx->currsch]));
|
||||
vhdl_netlist(fd, vhdl_stop);
|
||||
err |= vhdl_netlist(fd, vhdl_stop);
|
||||
fprintf(fd,"//// begin user architecture code\n");
|
||||
|
||||
for(l=0;l<xctx->instances; ++l) {
|
||||
|
|
@ -729,5 +732,6 @@ void vhdl_block_netlist(FILE *fd, int i)
|
|||
if(debug_var==0) xunlink(netl_filename);
|
||||
}
|
||||
xctx->netlist_count++;
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
|
|||
18
src/xschem.h
18
src/xschem.h
|
|
@ -1261,13 +1261,13 @@ extern void store_arc(int pos, double x, double y, double r, double a, double b,
|
|||
unsigned int rectcolor, unsigned short sel, char *prop_ptr);
|
||||
|
||||
extern void hier_psprint(char **res, int what);
|
||||
extern void global_spice_netlist(int global);
|
||||
extern void global_tedax_netlist(int global);
|
||||
extern void global_vhdl_netlist(int global);
|
||||
extern void global_verilog_netlist(int global);
|
||||
extern void vhdl_block_netlist(FILE *fd, int i);
|
||||
extern void verilog_block_netlist(FILE *fd, int i);
|
||||
extern void spice_block_netlist(FILE *fd, int i);
|
||||
extern int global_spice_netlist(int global);
|
||||
extern int global_tedax_netlist(int global);
|
||||
extern int global_vhdl_netlist(int global);
|
||||
extern int global_verilog_netlist(int global);
|
||||
extern int vhdl_block_netlist(FILE *fd, int i);
|
||||
extern int verilog_block_netlist(FILE *fd, int i);
|
||||
extern int spice_block_netlist(FILE *fd, int i);
|
||||
extern void remove_symbols(void);
|
||||
extern void remove_symbol(int i);
|
||||
extern void clear_drawing(void);
|
||||
|
|
@ -1441,7 +1441,7 @@ extern int record_global_node(int what, FILE *fp, char *node);
|
|||
extern int count_items(const char *s, const char *sep, const char *quote);
|
||||
extern int get_unnamed_node(int what, int mult, int node);
|
||||
extern void node_hash_free(void);
|
||||
extern void traverse_node_hash();
|
||||
extern int traverse_node_hash();
|
||||
extern Node_hashentry
|
||||
*bus_node_hash_lookup(const char *token, const char *dir,int what, int port, char *sig_type,
|
||||
char *verilog_type, char *value, char *class);
|
||||
|
|
@ -1462,7 +1462,7 @@ extern void draw_hilight_net(int on_window);
|
|||
extern void display_hilights(char **str);
|
||||
extern void redraw_hilights(int clear);
|
||||
extern void set_tcl_netlist_type(void);
|
||||
extern void prepare_netlist_structs(int for_netlist);
|
||||
extern int prepare_netlist_structs(int for_netlist);
|
||||
extern int compare_schematics(const char *filename);
|
||||
extern int warning_overlapped_symbols(int sel);
|
||||
extern void free_simdata(void);
|
||||
|
|
|
|||
|
|
@ -215,39 +215,35 @@ proc execute_fileevent {id} {
|
|||
global execute
|
||||
append execute(data,$id) [read $execute(pipe,$id) 1024]
|
||||
if {[eof $execute(pipe,$id)]} {
|
||||
set report [regexp {1} $execute(status,$id)]
|
||||
fileevent $execute(pipe,$id) readable ""
|
||||
if { [regexp {1} $execute(status,$id)] } {
|
||||
# setting pipe to blocking before closing allows to see if pipeline failed
|
||||
# do not ask status for processes that close stdout/stderr, as eof might
|
||||
# occur before process ends and following close blocks until process terminates.
|
||||
fconfigure $execute(pipe,$id) -blocking 1
|
||||
set status 0
|
||||
if { [ info tclversion] > 8.4} {
|
||||
set catch_return [eval catch [list {close $execute(pipe,$id)} err options] ]
|
||||
} else {
|
||||
set catch_return [eval catch [list {close $execute(pipe,$id)} err] ]
|
||||
}
|
||||
if {$catch_return} {
|
||||
if {[info tclversion] > 8.4} {
|
||||
set details [dict get $options -errorcode]
|
||||
if {[lindex $details 0] eq "CHILDSTATUS"} {
|
||||
set status [lindex $details 2]
|
||||
viewdata "Failed: $execute(cmd,$id)\nstderr:\n$err\ndata:\n$execute(data,$id)"
|
||||
} else {
|
||||
set status 1
|
||||
viewdata "Completed: $execute(cmd,$id)\nstderr:\n$err\ndata:\n$execute(data,$id)"
|
||||
}
|
||||
# setting pipe to blocking before closing allows to see if pipeline failed
|
||||
# do not ask status for processes that close stdout/stderr, as eof might
|
||||
# occur before process ends and following close blocks until process terminates.
|
||||
fconfigure $execute(pipe,$id) -blocking 1
|
||||
set status 0
|
||||
if { [ info tclversion] > 8.4} {
|
||||
set catch_return [eval catch [list {close $execute(pipe,$id)} err options] ]
|
||||
} else {
|
||||
set catch_return [eval catch [list {close $execute(pipe,$id)} err] ]
|
||||
}
|
||||
if {$catch_return} {
|
||||
if {[info tclversion] > 8.4} {
|
||||
set details [dict get $options -errorcode]
|
||||
if {[lindex $details 0] eq "CHILDSTATUS"} {
|
||||
set status [lindex $details 2]
|
||||
if {$report} {viewdata "Failed: $execute(cmd,$id)\nstderr:\n$err\ndata:\n$execute(data,$id)"}
|
||||
} else {
|
||||
set status 1
|
||||
viewdata "Completed: $execute(cmd,$id)\nstderr:\n$err\ndata:\n$execute(data,$id)"
|
||||
if {$report} {viewdata "Completed: $execute(cmd,$id)\nstderr:\n$err\ndata:\n$execute(data,$id)"}
|
||||
}
|
||||
} else {
|
||||
set status 1
|
||||
if {$report} {viewdata "Completed: $execute(cmd,$id)\nstderr:\n$err\ndata:\n$execute(data,$id)"}
|
||||
}
|
||||
if {$status == 0} {
|
||||
viewdata "Completed: $execute(cmd,$id)\ndata:\n$execute(data,$id)"
|
||||
}
|
||||
} else {
|
||||
# nonblocking close always succeed
|
||||
close $execute(pipe,$id)
|
||||
}
|
||||
if {$status == 0} {
|
||||
if {$report} {viewdata "Completed: $execute(cmd,$id)\ndata:\n$execute(data,$id)"}
|
||||
}
|
||||
if {[info exists execute(callback,$id)] && $execute(callback,$id) ne {}} {
|
||||
uplevel #0 "eval $execute(callback,$id)"
|
||||
|
|
@ -255,7 +251,9 @@ proc execute_fileevent {id} {
|
|||
}
|
||||
set execute(cmd,last) $execute(cmd,$id)
|
||||
set execute(data,last) $execute(data,$id)
|
||||
set execute(error,last) $err
|
||||
set execute(status,last) $execute(status,$id)
|
||||
set execute(exitcode,last) $status
|
||||
unset execute(pipe,$id)
|
||||
unset execute(data,$id)
|
||||
unset execute(status,$id)
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
v {xschem version=2.9.8 file_version=1.2}
|
||||
v {xschem version=3.1.0 file_version=1.2
|
||||
}
|
||||
G {process
|
||||
begin
|
||||
if now = 0 ns then
|
||||
|
|
@ -172,3 +173,4 @@ use ieee.std_logic_unsigned.all;
|
|||
|
||||
|
||||
}
|
||||
C {noconn.sym} 90 -200 0 1 {name=l1}
|
||||
|
|
|
|||
|
|
@ -360,3 +360,13 @@ signal V_VX, V_VX2, V_VXS, V_SP: real;
|
|||
|
||||
}
|
||||
C {lab_wire.sym} 430 -680 0 1 {name=l1 lab=VX sig_type=rrreal }
|
||||
C {lab_pin.sym} 110 -500 0 0 { name=p1 lab=SW2 }
|
||||
C {lab_pin.sym} 110 -520 0 0 { name=p2 lab=SW1 }
|
||||
C {lab_pin.sym} 110 -540 0 0 { name=p3 lab=SW }
|
||||
C {lab_pin.sym} 110 -560 0 0 { name=p4 lab=ING1 }
|
||||
C {lab_pin.sym} 110 -580 0 0 { name=p5 lab=ING }
|
||||
C {noconn.sym} 110 -580 0 1 {name=l10}
|
||||
C {noconn.sym} 110 -560 0 1 {name=l11}
|
||||
C {noconn.sym} 110 -540 0 1 {name=l12}
|
||||
C {noconn.sym} 110 -520 0 1 {name=l13}
|
||||
C {noconn.sym} 110 -500 0 1 {name=l14}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
v {xschem version=3.0.0 file_version=1.2 }
|
||||
v {xschem version=3.1.0 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
V {}
|
||||
|
|
@ -80,3 +81,9 @@ C {title.sym} 160 -30 0 0 {name=l2 author="Stefan Schippers"}
|
|||
C {opin.sym} 210 -160 0 0 {name=p5 lab=OUT}
|
||||
C {ipin.sym} 140 -210 0 0 {name=p1 lab=MINUS}
|
||||
C {ipin.sym} 140 -170 0 0 {name=p4 lab=VSS}
|
||||
C {noconn.sym} 140 -210 2 0 {name=l1}
|
||||
C {noconn.sym} 140 -190 2 0 {name=l3}
|
||||
C {noconn.sym} 140 -170 2 0 {name=l4}
|
||||
C {noconn.sym} 140 -150 2 0 {name=l5}
|
||||
C {noconn.sym} 140 -130 2 0 {name=l6}
|
||||
C {noconn.sym} 210 -160 2 1 {name=l7}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
v {xschem version=2.9.5_RC5 file_version=1.1}
|
||||
v {xschem version=3.1.0 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
V {}
|
||||
S {}
|
||||
E {}
|
||||
|
|
@ -39,3 +41,5 @@ C {capa.sym} 820 -250 0 0 {name=c1 m=1 value=1n}
|
|||
C {lab_pin.sym} 820 -220 0 0 {name=p5 lab=VSS}
|
||||
C {lab_pin.sym} 900 -220 0 0 {name=p6 lab=VSS}
|
||||
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"}
|
||||
C {noconn.sym} 520 -340 1 0 {name=l2}
|
||||
C {noconn.sym} 640 -370 2 0 {name=l3}
|
||||
|
|
|
|||
|
|
@ -18,8 +18,9 @@ x2=0.00025416
|
|||
divx=5
|
||||
subdivx=1
|
||||
node="out
|
||||
trig"
|
||||
color="4 15"
|
||||
trig
|
||||
ctrl"
|
||||
color="4 15 7"
|
||||
dataset=-1
|
||||
unitx=1
|
||||
logx=0
|
||||
|
|
@ -27,6 +28,8 @@ logy=0
|
|||
}
|
||||
T {NE555 TIMER IC EXAMPLE} 360 -490 0 0 0.4 0.4 {}
|
||||
N 130 -150 200 -150 {lab=TRIG}
|
||||
N 570 -130 570 -100 {
|
||||
lab=CTRL}
|
||||
C {code.sym} 710 -190 0 0 {
|
||||
name=STIMULI
|
||||
value=".option SCALE=1e-6 PARHIER=LOCAL RUNLVL=6 post MODMONTE=1
|
||||
|
|
@ -70,3 +73,4 @@ C {launcher.sym} 790 -290 0 0 {name=h5
|
|||
descr="load waves"
|
||||
tclcommand="xschem raw_read $netlist_dir/test_ne555.raw tran"
|
||||
}
|
||||
C {noconn.sym} 570 -130 2 0 {name=l2}
|
||||
|
|
|
|||
|
|
@ -19,8 +19,8 @@ C {bsource.sym} 450 -150 0 1 {name=B1 VAR=V FUNC="\{OFFSET + AMPLITUDE/2*(tanh(V
|
|||
}
|
||||
C {title.sym} 160 -30 0 0 {name=l3 author="Stefan Schippers"}
|
||||
C {res.sym} 570 -240 1 0 {name=R1
|
||||
value=ROUT
|
||||
value='ROUT'
|
||||
m=1}
|
||||
C {parax_cap.sym} 630 -230 0 0 {name=C3 gnd=0 value=COUT m=1}
|
||||
C {parax_cap.sym} 630 -230 0 0 {name=C3 gnd=0 value='COUT' m=1}
|
||||
C {vsource.sym} 150 -260 1 0 {name=V1 value=0}
|
||||
C {vsource.sym} 150 -210 1 0 {name=V2 value=0}
|
||||
|
|
|
|||
|
|
@ -160,7 +160,7 @@ T {Maximum Power} 327.5 -860 0 0 0.2 0.2 {layer=8}
|
|||
T {set between 0 and 1
|
||||
to simulate
|
||||
sun radiation
|
||||
level} 20 -350 0 0 0.2 0.2 {}
|
||||
level} 10 -390 0 0 0.2 0.2 {}
|
||||
N 1010 -160 1100 -160 {lab=0}
|
||||
N 1100 -250 1100 -160 {lab=0}
|
||||
N 640 -560 730 -560 {lab=#net1}
|
||||
|
|
@ -179,24 +179,24 @@ N 1100 -390 1140 -390 {lab=LED}
|
|||
N 1100 -390 1100 -310 {lab=LED}
|
||||
N 820 -380 820 -340 { lab=#net2}
|
||||
N 920 -560 940 -560 { lab=#net3}
|
||||
N 370 -440 370 -390 {
|
||||
N 360 -480 360 -430 {
|
||||
lab=#net4}
|
||||
N 370 -330 370 -280 {lab=0}
|
||||
N 370 -440 410 -440 {
|
||||
N 360 -370 360 -320 {lab=0}
|
||||
N 360 -480 400 -480 {
|
||||
lab=#net4}
|
||||
N 760 -670 760 -600 {
|
||||
lab=CTRL1}
|
||||
N 470 -440 540 -440 {
|
||||
N 460 -480 530 -480 {
|
||||
lab=#net5}
|
||||
N 600 -440 660 -440 {
|
||||
N 590 -480 650 -480 {
|
||||
lab=PANEL}
|
||||
N 510 -300 510 -280 {
|
||||
N 500 -340 500 -320 {
|
||||
lab=0}
|
||||
N 510 -380 510 -360 {
|
||||
N 500 -420 500 -400 {
|
||||
lab=#net6}
|
||||
N 170 -360 330 -360 {
|
||||
N 160 -400 320 -400 {
|
||||
lab=SUN}
|
||||
N 170 -270 170 -250 {
|
||||
N 160 -310 160 -290 {
|
||||
lab=0}
|
||||
N 610 -1010 610 -990 {
|
||||
lab=0}
|
||||
|
|
@ -214,7 +214,7 @@ N 550 -900 600 -900 {
|
|||
lab=LED}
|
||||
N 1010 -1000 1060 -1000 {
|
||||
lab=CTRL1}
|
||||
N 170 -360 170 -330 {
|
||||
N 160 -400 160 -370 {
|
||||
lab=SUN}
|
||||
N 830 -970 830 -870 {
|
||||
lab=LEVEL}
|
||||
|
|
@ -227,17 +227,19 @@ lab=TRIANG}
|
|||
N 820 -280 820 -160 {
|
||||
lab=0}
|
||||
C {title.sym} 160 -40 0 0 {name=l1 author="Stefan Schippers" net_name=true}
|
||||
C {code_shown.sym} 190 -200 0 0 {name=CONTROL value=".control
|
||||
save all
|
||||
C {code_shown.sym} 190 -250 0 0 {name=CONTROL value="* following line for batch mode...
|
||||
.tran .05u 1m uic
|
||||
* following block for interactive mode
|
||||
.control
|
||||
* save all
|
||||
tran .05u 1m uic
|
||||
write solar_panel.raw
|
||||
.endc
|
||||
|
||||
" net_name=true}
|
||||
C {code.sym} 20 -190 0 0 {name=MODELS value=".MODEL DIODE D(IS=1.139e-08 RS=0.99 CJO=9.3e-12 VJ=1.6 M=0.411 BV=30 EG=0.7 )
|
||||
.MODEL swmod SW(VT=0.5 VH=0.01 RON=0.01 ROFF=10000000)
|
||||
" net_name=true}
|
||||
C {lab_pin.sym} 660 -440 0 1 {name=l4 lab=PANEL }
|
||||
C {lab_pin.sym} 650 -480 0 1 {name=l4 lab=PANEL }
|
||||
C {lab_pin.sym} 630 -160 0 0 {name=l6 lab=0 }
|
||||
C {ammeter.sym} 1070 -390 3 0 {name=Vled net_name=true}
|
||||
C {ind.sym} 890 -560 3 1 {name=L2
|
||||
|
|
@ -274,7 +276,7 @@ C {isource_table.sym} 1100 -280 0 0 {name=G2[9..0] CTRL="V(LED)" TABLE="
|
|||
C {ammeter.sym} 610 -560 3 0 {name=Vsw net_name=true}
|
||||
C {ammeter.sym} 820 -310 2 0 {name=Vdiode net_name=true}
|
||||
C {spice_probe.sym} 1120 -390 0 0 {name=p1 analysis=tran}
|
||||
C {spice_probe.sym} 660 -440 0 0 {name=p2 analysis=tran}
|
||||
C {spice_probe.sym} 650 -480 0 0 {name=p2 analysis=tran}
|
||||
C {spice_probe.sym} 820 -460 0 1 {name=p3 analysis=tran}
|
||||
C {launcher.sym} 1080 -1140 0 0 {name=h3
|
||||
descr="Reload Waves"
|
||||
|
|
@ -282,22 +284,22 @@ tclcommand="
|
|||
xschem raw_read $netlist_dir/[file tail [file rootname [xschem get current_name]]].raw tran
|
||||
"
|
||||
}
|
||||
C {pv_ngspice.sym} 370 -360 0 0 {name=X1 m=1 power=100 n=36}
|
||||
C {lab_pin.sym} 370 -280 0 0 {name=l12 lab=0 }
|
||||
C {capa.sym} 510 -410 0 0 {name=C11
|
||||
C {pv_ngspice.sym} 360 -400 0 0 {name=X1 m=1 power=100 n=36}
|
||||
C {lab_pin.sym} 360 -320 0 0 {name=l12 lab=0 }
|
||||
C {capa.sym} 500 -450 0 0 {name=C11
|
||||
m=1
|
||||
value=10u
|
||||
footprint=1206
|
||||
device="ceramic capacitor" net_name=true}
|
||||
C {lab_pin.sym} 510 -280 0 0 {name=l90 lab=0 }
|
||||
C {ammeter.sym} 440 -440 3 1 {name=Vpanel net_name=true}
|
||||
C {lab_pin.sym} 500 -320 0 0 {name=l90 lab=0 }
|
||||
C {ammeter.sym} 430 -480 3 1 {name=Vpanel net_name=true}
|
||||
C {diode_ngspice.sym} 820 -410 2 0 {name=X2 m=1 Roff=1e9 Ron=0.1}
|
||||
C {switch_ngspice.sym} 760 -560 1 0 {name=S1 model=swmod}
|
||||
C {lab_pin.sym} 740 -600 0 0 {name=l5 lab=0 }
|
||||
C {ammeter.sym} 570 -440 3 1 {name=Vpanel1 net_name=true}
|
||||
C {ammeter.sym} 510 -330 0 0 {name=Vcap net_name=true}
|
||||
C {vsource.sym} 170 -300 0 0 {name=Vfade value="pwl 0 1 1m 0"}
|
||||
C {lab_pin.sym} 170 -250 0 0 {name=l8 lab=0 }
|
||||
C {ammeter.sym} 560 -480 3 1 {name=Vpanel1 net_name=true}
|
||||
C {ammeter.sym} 500 -370 0 0 {name=Vcap net_name=true}
|
||||
C {vsource.sym} 160 -340 0 0 {name=Vfade value="pwl 0 1 1m 0"}
|
||||
C {lab_pin.sym} 160 -290 0 0 {name=l8 lab=0 }
|
||||
C {ngspice_get_expr.sym} 1120 -320 0 0 {name=r29
|
||||
node="[format %.4g [expr \{[ngspice::get_voltage led] * [ngspice::get_current vled]\}]] W"
|
||||
descr = power
|
||||
|
|
@ -316,4 +318,7 @@ C {lab_pin.sym} 550 -900 0 0 {name=l15 lab=LED }
|
|||
C {lab_pin.sym} 830 -870 0 1 {name=l18 lab=LEVEL}
|
||||
C {comp_ngspice.sym} 950 -1000 0 0 {name=x4 OFFSET=0.5 AMPLITUDE=1 ROUT=1 COUT=1p}
|
||||
C {lab_pin.sym} 1060 -1000 0 1 {name=l19 lab=CTRL1 }
|
||||
C {lab_pin.sym} 170 -360 0 0 {name=l20 lab=SUN }
|
||||
C {lab_pin.sym} 160 -400 0 0 {name=l20 lab=SUN }
|
||||
C {spice_probe.sym} 850 -1030 0 1 {name=p4 analysis=tran}
|
||||
C {spice_probe.sym} 810 -870 0 1 {name=p5 analysis=tran}
|
||||
C {spice_probe.sym} 760 -620 0 0 {name=p6 analysis=tran}
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
v {xschem version=2.9.9 file_version=1.2 }
|
||||
v {xschem version=3.1.0 file_version=1.2
|
||||
}
|
||||
G {}
|
||||
K {}
|
||||
V {// these are the stimulus parameters
|
||||
|
|
@ -1511,8 +1512,8 @@ N 420 -290 450 -290 {lab=A}
|
|||
N 480 -410 480 -390 {lab=EN}
|
||||
N 420 -410 480 -410 {lab=EN}
|
||||
N 510 -290 540 -290 {lab=Z}
|
||||
N 480 -350 480 -340 {lab=VDDPIN}
|
||||
N 480 -180 480 -170 {lab=GNDPIN}
|
||||
N 480 -350 480 -320 {lab=VCCPIN}
|
||||
N 480 -210 480 -170 {lab=VSSPIN}
|
||||
C {p.sym} 480 -370 3 1 {name=m60 model=cmosp w=WP l=2.4u m=1
|
||||
}
|
||||
C {n.sym} 480 -150 3 0 {name=m1 model=cmosn w=WN l=2.4u m=1}
|
||||
|
|
@ -1520,6 +1521,8 @@ C {iopin.sym} 540 -290 0 0 {name=p1 lab=Z}
|
|||
C {iopin.sym} 420 -290 0 1 {name=p2 lab=A}
|
||||
C {ipin.sym} 420 -410 0 0 {name=p3 lab=EN}
|
||||
C {ipin.sym} 420 -110 0 0 {name=p4 lab=E}
|
||||
C {lab_pin.sym} 480 -340 3 0 {name=l1 sig_type=std_logic lab=VCCPIN}
|
||||
C {lab_pin.sym} 480 -180 3 1 {name=l2 sig_type=std_logic lab=VSSPIN}
|
||||
C {lab_pin.sym} 480 -320 3 0 {name=l1 sig_type=std_logic lab=VCCPIN}
|
||||
C {lab_pin.sym} 480 -210 3 1 {name=l2 sig_type=std_logic lab=VSSPIN}
|
||||
C {title.sym} 160 0 0 0 {name=l3 author="Stefan Schippers"}
|
||||
C {noconn.sym} 480 -210 2 0 {name=l4}
|
||||
C {noconn.sym} 480 -320 2 0 {name=l5}
|
||||
|
|
|
|||
Loading…
Reference in New Issue