fixed a hypotetical integer overflow issue, do increment and modulo of hilight_color , remove some spaghetti code (use propagate_hilights() )

This commit is contained in:
Stefan Frederik 2021-01-08 21:25:11 +01:00
parent d9bfbff26f
commit 2063b42613
16 changed files with 84 additions and 127 deletions

View File

@ -1204,12 +1204,11 @@ void calc_drawing_bbox(xRect *boundbox, int selected)
boundbox->x2=100;
boundbox->y1=-100;
boundbox->y2=100;
for(c=0;c<cadlayers;c++)
if(selected != 2) for(c=0;c<cadlayers;c++)
{
for(i=0;i<xctx->lines[c];i++)
{
if(selected == 1 && !xctx->line[c][i].sel) continue;
if(selected == 2) continue;
tmp.x1=xctx->line[c][i].x1;
tmp.x2=xctx->line[c][i].x2;
tmp.y1=xctx->line[c][i].y1;
@ -1223,7 +1222,6 @@ void calc_drawing_bbox(xRect *boundbox, int selected)
double x1=0., y1=0., x2=0., y2=0.;
int k;
if(selected == 1 && !xctx->poly[c][i].sel) continue;
if(selected == 2) continue;
count++;
for(k=0; k<xctx->poly[c][i].points; k++) {
/* fprintf(errfp, " poly: point %d: %.16g %.16g\n", k, pp[c][i].x[k], pp[c][i].y[k]); */
@ -1239,7 +1237,6 @@ void calc_drawing_bbox(xRect *boundbox, int selected)
for(i=0;i<xctx->arcs[c];i++)
{
if(selected == 1 && !xctx->arc[c][i].sel) continue;
if(selected == 2) continue;
arc_bbox(xctx->arc[c][i].x, xctx->arc[c][i].y, xctx->arc[c][i].r, xctx->arc[c][i].a, xctx->arc[c][i].b,
&tmp.x1, &tmp.y1, &tmp.x2, &tmp.y2);
count++;
@ -1249,7 +1246,6 @@ void calc_drawing_bbox(xRect *boundbox, int selected)
for(i=0;i<xctx->rects[c];i++)
{
if(selected == 1 && !xctx->rect[c][i].sel) continue;
if(selected == 2) continue;
tmp.x1=xctx->rect[c][i].x1;
tmp.x2=xctx->rect[c][i].x2;
tmp.y1=xctx->rect[c][i].y1;
@ -1283,11 +1279,10 @@ void calc_drawing_bbox(xRect *boundbox, int selected)
count++;
updatebbox(count,boundbox,&tmp);
}
if(has_x) for(i=0;i<xctx->texts;i++)
if(has_x && selected != 2) for(i=0;i<xctx->texts;i++)
{
int no_of_lines, longest_line;
if(selected == 1 && !xctx->text[i].sel) continue;
if(selected == 2) continue;
#if HAS_CAIRO==1
customfont = set_text_custom_font(&xctx->text[i]);
#endif
@ -1660,15 +1655,10 @@ void new_wire(int what, double mx_snap, double my_snap)
xctx->prep_hi_structs = 0;
if(autotrim_wires) trim_wires();
update_conn_cues(1,1);
if( xctx->hilight_nets || show_pin_net_names) prepare_netlist_structs(0);
if(show_pin_net_names || xctx->hilight_nets) prepare_netlist_structs(0);
if(!big) {
/* xRect boundbox; */
bbox(START , 0.0 , 0.0 , 0.0 , 0.0);
#if 0
if( xctx->hilight_nets ) calc_drawing_bbox(&boundbox, 2);
bbox(ADD, boundbox.x1, boundbox.y1, boundbox.x2, boundbox.y2);
#endif
if(show_pin_net_names || xctx->hilight_nets) {
if(show_pin_net_names || xctx->hilight_nets) {
int_hash_lookup(xctx->node_redraw_table, xctx->wire[xctx->wires-1].node, 0, XINSERT_NOREPLACE);
find_inst_to_be_redrawn();
}

View File

@ -165,6 +165,7 @@ int callback(int event, int mx, int my, KeySym key,
my_snprintf(str, S(str), "mouse = %.16g %.16g - selected: %d path: %s",
xctx->mousex_snap, xctx->mousey_snap, xctx->lastsel, xctx->sch_path[xctx->currsch] );
statusmsg(str,1);
switch(event)
{
case EnterNotify:
@ -955,7 +956,7 @@ int callback(int event, int mx, int my, KeySym key,
if(xctx->semaphore >= 2) break;
enable_drill=1;
hilight_net(0);
redraw_hilights();
redraw_hilights(0);
/* draw_hilight_net(1); */
break;
}
@ -964,7 +965,7 @@ int callback(int event, int mx, int my, KeySym key,
if(xctx->semaphore >= 2) break;
enable_drill=0;
hilight_net(0);
redraw_hilights();
redraw_hilights(0);
/* draw_hilight_net(1); */
break;
}
@ -990,7 +991,7 @@ int callback(int event, int mx, int my, KeySym key,
if(xctx->semaphore >= 2) break;
enable_drill=0;
hilight_net(GAW);
redraw_hilights();
redraw_hilights(0);
break;
}
if(key=='g' && state==0) /* half snap factor */
@ -1665,27 +1666,16 @@ int callback(int event, int mx, int my, KeySym key,
launcher();
}
if( !(state & ShiftMask) ) {
xRect boundbox;
if(auto_hilight && xctx->hilight_nets && sel == 0 ) { /* 20160413 20160503 */
if(!prev_last_sel) {
int big = xctx->wires> 2000 || xctx->instances > 2000 ;
if(!big) calc_drawing_bbox(&boundbox, 2);
clear_all_hilights();
/* undraw_hilight_net(1); */
if(!big) {
bbox(START, 0.0 , 0.0 , 0.0 , 0.0);
bbox(ADD, boundbox.x1, boundbox.y1, boundbox.x2, boundbox.y2);
bbox(SET , 0.0 , 0.0 , 0.0 , 0.0);
}
draw();
if(!big) bbox(END , 0.0 , 0.0 , 0.0 , 0.0);
redraw_hilights(1); /* 1: clear all hilights, then draw */
}
}
}
if(auto_hilight) {
hilight_net(0);
if(xctx->lastsel) {
redraw_hilights();
redraw_hilights(0);
/* draw_hilight_net(1); */
}
}

View File

@ -958,7 +958,7 @@ void update_symbol(const char *result, int x)
if(xctx->sel_array[k].type!=ELEMENT) continue;
i=xctx->sel_array[k].n;
if(show_pin_net_names) {
if(show_pin_net_names || xctx->hilight_nets) {
int j;
prepare_netlist_structs(0);
for(j = 0; j < (xctx->inst[i].ptr + xctx->sym)->rects[PINLAYER]; j++) {
@ -966,6 +966,7 @@ void update_symbol(const char *result, int x)
int_hash_lookup(xctx->node_redraw_table, xctx->inst[i].node[j], 0, XINSERT_NOREPLACE);
}
}
find_inst_to_be_redrawn();
}
/* 20171220 calculate bbox before changes to correctly redraw areas */
@ -1043,19 +1044,14 @@ void update_symbol(const char *result, int x)
xctx->prep_hash_inst=0;
xctx->prep_net_structs=0;
xctx->prep_hi_structs=0;
if(show_pin_net_names || xctx->hilight_nets) prepare_netlist_structs(0);
for(k=0;k<xctx->lastsel;k++) {
if(xctx->sel_array[k].type!=ELEMENT) continue;
i=xctx->sel_array[k].n;
type=xctx->sym[xctx->inst[i].ptr].type;
symbol_bbox(i, &xctx->inst[i].x1, &xctx->inst[i].y1, &xctx->inst[i].x2, &xctx->inst[i].y2);
bbox(ADD, xctx->inst[i].x1, xctx->inst[i].y1, xctx->inst[i].x2, xctx->inst[i].y2);
/* in case of net hilights, when changing 'lab' of net labels/pins we must re-run
prepare_netlist_structs() so the .node field of that instance will be reset
and drawn back unhilighted .
|
\|/ */
if((show_pin_net_names || xctx->hilight_nets) && type && IS_LABEL_OR_PIN(type)) {
prepare_netlist_structs(0);
for(j = 0; j < (xctx->inst[i].ptr + xctx->sym)->rects[PINLAYER]; j++) { /* <<< only .node[0] ? */
if( xctx->inst[i].node && xctx->inst[i].node[j]) {
int_hash_lookup(xctx->node_redraw_table, xctx->inst[i].node[j], 0, XINSERT_NOREPLACE);
@ -1063,16 +1059,11 @@ void update_symbol(const char *result, int x)
}
}
}
if(xctx->hilight_nets) for(i=0; i < xctx->instances; i++) {
char *type = (xctx->inst[i].ptr+ xctx->sym)->type;
if(type && xctx->inst[i].node && IS_LABEL_SH_OR_PIN(type)) {
if(!bus_hilight_lookup( xctx->inst[i].node[0], 0, XLOOKUP)) {
xctx->inst[i].color = -10000;
}
}
if(xctx->hilight_nets) {
propagate_hilights(1, 1, XINSERT_NOREPLACE);
}
if(show_pin_net_names || xctx->hilight_nets) find_inst_to_be_redrawn();
}
if(show_pin_net_names || xctx->hilight_nets) find_inst_to_be_redrawn();
/* redraw symbol with new props */
bbox(SET,0.0,0.0,0.0,0.0);
dbg(1, "update_symbol(): redrawing inst_ptr.txtprop string\n");

View File

@ -102,13 +102,14 @@ void free_hilight_hash(void) /* remove the whole hash table */
* active_layer[2] = 10 if 9 is disabled it is skipped
* ...
* if a layer is disabled (not viewable) it is skipped
* active layers is the total number of layers for hilights.
* n_active_layers is the total number of layers for hilights.
* standard xschem conf: cadlayers=22, n_active_layers=15 if no disabled layers.
*/
int get_color(int value)
{
int x;
if(value < 0) return -value;
if(value < 0) return (-value) % cadlayers ;
if(n_active_layers) {
x = value%(n_active_layers);
return active_layer[x];
@ -117,6 +118,12 @@ int get_color(int value)
}
}
void incr_hilight_color(void)
{
xctx->hilight_color = (xctx->hilight_color + 1) % (n_active_layers * cadlayers);
}
/* print all highlight signals which are not ports (in/out/inout). */
void create_plot_cmd(int viewer)
{
@ -342,7 +349,7 @@ void hilight_net_pin_mismatches(void)
if(netname && strcmp(lab, netname)) {
dbg(1, "hilight_net_pin_mismatches(): hilight: %s\n", netname);
bus_hilight_lookup(netname, xctx->hilight_color, XINSERT_NOREPLACE);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
}
}
@ -352,7 +359,7 @@ void hilight_net_pin_mismatches(void)
my_free(715, &lab);
my_free(716, &netname);
propagate_hilights(1, 0, XINSERT_NOREPLACE);
redraw_hilights();
redraw_hilights(0);
}
void hilight_parent_pins(void)
@ -498,7 +505,7 @@ int search(const char *tok, const char *val, int sub, int sel)
dbg(1, "search():val=%s\n", val);
if(!sel) {
col=xctx->hilight_color;
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
}
has_token = 0;
prepare_netlist_structs(0);
@ -655,7 +662,7 @@ int search(const char *tok, const char *val, int sub, int sel)
rebuild_selected_array(); /* sets or clears xctx->ui_state SELECTION flag */
draw_selection(gc[SELLAYER], 0);
}
else redraw_hilights();
else redraw_hilights(0);
}
#ifdef __unix__
regfree(&re);
@ -736,9 +743,9 @@ int hilight_netname(const char *name)
node_entry = bus_hash_lookup(name, "", XLOOKUP, 0, "", "", "", "");
/* sets xctx->hilight_nets=1 */
if(node_entry && !bus_hilight_lookup(name, xctx->hilight_color, XINSERT_NOREPLACE)) {
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
propagate_hilights(1, 0, XINSERT_NOREPLACE);
redraw_hilights();
redraw_hilights(0);
}
return node_entry ? 1 : 0;
}
@ -1216,7 +1223,7 @@ void hilight_net(int to_waveform)
/* sets xctx->hilight_nets=1 */
if(!bus_hilight_lookup(xctx->wire[n].node, xctx->hilight_color, XINSERT_NOREPLACE)) {
if(to_waveform == GAW) send_net_to_gaw(sim_is_xyce, xctx->wire[n].node);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
}
break;
case ELEMENT:
@ -1225,13 +1232,13 @@ void hilight_net(int to_waveform)
/* sets xctx->hilight_nets=1 */
if(!bus_hilight_lookup(xctx->inst[n].node[0], xctx->hilight_color, XINSERT_NOREPLACE)) {
if(to_waveform == GAW) send_net_to_gaw(sim_is_xyce, xctx->inst[n].node[0]);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
}
} else {
dbg(1, "hilight_net(): setting hilight flag on inst %d\n",n);
xctx->hilight_nets=1;
xctx->inst[n].color = xctx->hilight_color;
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
}
if(type && (!strcmp(type, "current_probe") || !strcmp(type, "vsource")) ) {
if(to_waveform == GAW) send_current_to_gaw(sim_is_xyce, xctx->inst[n].instname);
@ -1241,7 +1248,7 @@ void hilight_net(int to_waveform)
break;
}
}
if(!incr_hilight) xctx->hilight_color++;
if(!incr_hilight) incr_hilight_color();
propagate_hilights(1, 0, XINSERT_NOREPLACE);
tcleval("if { [info exists gaw_fd] } {close $gaw_fd; unset gaw_fd}\n");
}
@ -1287,13 +1294,14 @@ void unhilight_net(void)
}
/* redraws the whole affected rectangle, this avoids artifacts due to antialiased text */
void redraw_hilights(void)
void redraw_hilights(int clear)
{
xRect boundbox;
int big = xctx->wires> 2000 || xctx->instances > 2000 ;
if(!has_x) return;
if(!big) calc_drawing_bbox(&boundbox, 2);
if(clear) clear_all_hilights();
if(!big) {
calc_drawing_bbox(&boundbox, 2);
bbox(START, 0.0 , 0.0 , 0.0 , 0.0);
bbox(ADD, boundbox.x1, boundbox.y1, boundbox.x2, boundbox.y2);
bbox(SET , 0.0 , 0.0 , 0.0 , 0.0);
@ -1346,7 +1354,7 @@ void select_hilight_net(void)
}
xctx->need_reb_sel_arr = 1;
rebuild_selected_array(); /* sets or clears xctx->ui_state SELECTION flag */
redraw_hilights();
redraw_hilights(0);
}

View File

@ -931,7 +931,7 @@ void copy_objects(int what)
char *type=xctx->sym[xctx->inst[n].ptr].type;
symbol_bbox(n, &xctx->inst[n].x1, &xctx->inst[n].y1, &xctx->inst[n].x2, &xctx->inst[n].y2 );
bbox(ADD, xctx->inst[n].x1, xctx->inst[n].y1, xctx->inst[n].x2, xctx->inst[n].y2 );
if((xctx->hilight_nets || show_pin_net_names) && type && IS_LABEL_OR_PIN(type)) {
if((show_pin_net_names || xctx->hilight_nets) && type && IS_LABEL_OR_PIN(type)) {
for(p = 0; p < (xctx->inst[n].ptr + xctx->sym)->rects[PINLAYER]; p++) {
if( xctx->inst[n].node && xctx->inst[n].node[p]) {
int_hash_lookup(xctx->node_redraw_table, xctx->inst[n].node[p], 0, XINSERT_NOREPLACE);
@ -939,11 +939,11 @@ void copy_objects(int what)
}
}
}
if( (xctx->hilight_nets || show_pin_net_names) && xctx->sel_array[i].type == WIRE) {
if((show_pin_net_names || xctx->hilight_nets) && xctx->sel_array[i].type == WIRE) {
int_hash_lookup(xctx->node_redraw_table, xctx->wire[n].node, 0, XINSERT_NOREPLACE);
}
} /* for(i = 0; i < xctx->lastsel; i++) */
if( xctx->hilight_nets || show_pin_net_names) find_inst_to_be_redrawn();
if(show_pin_net_names || xctx->hilight_nets) find_inst_to_be_redrawn();
check_collapsing_objects();
if(autotrim_wires) trim_wires();
update_conn_cues(1, 1);
@ -1043,7 +1043,7 @@ void move_objects(int what, int merge, double dx, double dy)
char *type=xctx->sym[xctx->inst[n].ptr].type;
symbol_bbox(n, &inst[n].x1, &inst[n].y1, &inst[n].x2, &inst[n].y2 );
bbox(ADD, inst[n].x1, inst[n].y1, inst[n].x2, inst[n].y2 );
if((xctx->hilight_nets || show_pin_net_names) && type && IS_LABEL_OR_PIN(type)) {
if((show_pin_net_names || xctx->hilight_nets) && type && IS_LABEL_OR_PIN(type)) {
for(p = 0; p < (inst[n].ptr + xctx->sym)->rects[PINLAYER]; p++) {
if( inst[n].node && inst[n].node[p]) {
int_hash_lookup(xctx->node_redraw_table, xctx->inst[n].node[p], 0, XINSERT_NOREPLACE);
@ -1051,11 +1051,11 @@ void move_objects(int what, int merge, double dx, double dy)
}
}
}
if((xctx->hilight_nets || show_pin_net_names) && xctx->sel_array[i].type == WIRE) {
if((show_pin_net_names || xctx->hilight_nets) && xctx->sel_array[i].type == WIRE) {
int_hash_lookup(xctx->node_redraw_table, xctx->wire[n].node, 0, XINSERT_NOREPLACE);
}
}
if( xctx->hilight_nets || show_pin_net_names) find_inst_to_be_redrawn();
if(show_pin_net_names || xctx->hilight_nets) find_inst_to_be_redrawn();
for(k=0;k<cadlayers;k++)
{
for(i=0;i<xctx->lastsel;i++)
@ -1467,7 +1467,7 @@ void move_objects(int what, int merge, double dx, double dy)
char *type=xctx->sym[xctx->inst[n].ptr].type;
symbol_bbox(n, &inst[n].x1, &inst[n].y1, &inst[n].x2, &inst[n].y2 );
bbox(ADD, inst[n].x1, inst[n].y1, inst[n].x2, inst[n].y2 );
if((xctx->hilight_nets || show_pin_net_names) && type && IS_LABEL_OR_PIN(type)) {
if((show_pin_net_names || xctx->hilight_nets) && type && IS_LABEL_OR_PIN(type)) {
for(p = 0; p < (inst[n].ptr + xctx->sym)->rects[PINLAYER]; p++) {
if( inst[n].node && inst[n].node[p]) {
int_hash_lookup(xctx->node_redraw_table, xctx->inst[n].node[p], 0, XINSERT_NOREPLACE);
@ -1475,30 +1475,19 @@ void move_objects(int what, int merge, double dx, double dy)
}
}
}
if((xctx->hilight_nets || show_pin_net_names) && xctx->sel_array[i].type == WIRE) {
if((show_pin_net_names || xctx->hilight_nets) && xctx->sel_array[i].type == WIRE) {
int_hash_lookup(xctx->node_redraw_table, xctx->wire[n].node, 0, XINSERT_NOREPLACE);
}
}
if(xctx->hilight_nets || show_pin_net_names) find_inst_to_be_redrawn();
if(show_pin_net_names || xctx->hilight_nets) find_inst_to_be_redrawn();
check_collapsing_objects();
if(autotrim_wires) trim_wires();
update_conn_cues(1, 1);
if(xctx->hilight_nets) {
prepare_netlist_structs(0);
for(i=0; i < xctx->instances; i++) {
char *type = (xctx->inst[i].ptr+ xctx->sym)->type;
if(type && xctx->inst[i].node && IS_LABEL_SH_OR_PIN(type)) {
if(!bus_hilight_lookup( xctx->inst[i].node[0], 0, XLOOKUP)) {
xctx->inst[i].color = -10000;
}
}
}
propagate_hilights(1, 1, XINSERT_NOREPLACE);
}
xctx->ui_state &= ~STARTMOVE;
if(xctx->ui_state & STARTMERGE) xctx->ui_state |= SELECTION; /* leave selection state so objects can be deleted */
xctx->ui_state &= ~STARTMERGE;

View File

@ -442,9 +442,9 @@ static void signal_short( char *n1, char *n2)
statusmsg(str,2);
if(!netlist_count) {
bus_hilight_lookup(n1, xctx->hilight_color, XINSERT);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
bus_hilight_lookup(n2, xctx->hilight_color, XINSERT);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
}
}
}

View File

@ -315,35 +315,35 @@ void traverse_node_hash()
{
my_snprintf(str, S(str), "open net: %s", entry->token);
if(!netlist_count) bus_hilight_lookup(entry->token, xctx->hilight_color, XINSERT_NOREPLACE);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
statusmsg(str,2);
}
else if(entry->d.out ==0 && entry->d.inout == 0)
{
my_snprintf(str, S(str), "undriven node: %s", entry->token);
if(!netlist_count) bus_hilight_lookup(entry->token, xctx->hilight_color, XINSERT_NOREPLACE);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
statusmsg(str,2);
}
else if(entry->d.out >=2 && entry->d.port>=0) /* era d.port>=2 03102001 */
{
my_snprintf(str, S(str), "shorted output node: %s", entry->token);
if(!netlist_count) bus_hilight_lookup(entry->token, xctx->hilight_color, XINSERT_NOREPLACE);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
statusmsg(str,2);
}
else if(entry->d.in ==0 && entry->d.inout == 0)
{
my_snprintf(str, S(str), "node: %s goes nowhere", entry->token);
if(!netlist_count) bus_hilight_lookup(entry->token, xctx->hilight_color, XINSERT_NOREPLACE);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
statusmsg(str,2);
}
else if(entry->d.out >=2 && entry->d.inout == 0 && entry->d.port>=0) /* era d.port>=2 03102001 */
{
my_snprintf(str, S(str), "shorted output node: %s", entry->token);
if(!netlist_count) bus_hilight_lookup(entry->token, xctx->hilight_color, XINSERT_NOREPLACE);
if(incr_hilight) xctx->hilight_color++;
if(incr_hilight) incr_hilight_color();
statusmsg(str,2);
}
}

View File

@ -690,13 +690,10 @@ void ps_draw(void)
old_grid=draw_grid;
draw_grid=0;
/* calc_drawing_bbox(&boundbox, 0); ---.
* |
* \|/ */
boundbox.x1 = xctx->areax1; /* X_TO_PS(boundbox.x1); */
boundbox.x2 = xctx->areax2; /* X_TO_PS(boundbox.x2); */
boundbox.y1 = xctx->areay1; /* Y_TO_PS(boundbox.y1); */
boundbox.y2 = xctx->areay2; /* Y_TO_PS(boundbox.y2); */
boundbox.x1 = xctx->areax1;
boundbox.x2 = xctx->areax2;
boundbox.y1 = xctx->areay1;
boundbox.y2 = xctx->areay2;
dx=boundbox.x2-boundbox.x1;
dy=boundbox.y2-boundbox.y1;

View File

@ -1066,7 +1066,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
if(argc >=3 && !strcmp(argv[2], "drill")) enable_drill = 1;
hilight_net(0);
/* draw_hilight_net(1); */
redraw_hilights();
redraw_hilights(0);
Tcl_ResetResult(interp);
}
@ -2121,7 +2121,7 @@ int xschem(ClientData clientdata, Tcl_Interp *interp, int argc, const char * arg
enable_drill = 0;
hilight_net(GAW);
/* draw_hilight_net(1); */
redraw_hilights();
redraw_hilights(0);
Tcl_ResetResult(interp);
}

View File

@ -339,9 +339,7 @@ void delete(void)
* xctx->prep_net_structs=0;
* xctx->prep_hi_structs=0;
*/
if(show_pin_net_names) {
prepare_netlist_structs(0);
}
if((show_pin_net_names || xctx->hilight_nets)) prepare_netlist_structs(0);
for(i = 0; i < xctx->lastsel; i++) {
n = xctx->sel_array[i].n;
if(xctx->sel_array[i].type == ELEMENT) {
@ -349,7 +347,7 @@ void delete(void)
char *type = (xctx->inst[n].ptr + xctx->sym)->type;
symbol_bbox(n, &xctx->inst[n].x1, &xctx->inst[n].y1, &xctx->inst[n].x2, &xctx->inst[n].y2 );
bbox(ADD, xctx->inst[n].x1, xctx->inst[n].y1, xctx->inst[n].x2, xctx->inst[n].y2 );
if((xctx->hilight_nets || show_pin_net_names) && type && IS_LABEL_OR_PIN(type) ) {
if((show_pin_net_names || xctx->hilight_nets) && type && IS_LABEL_OR_PIN(type) ) {
for(p = 0; p < (xctx->inst[n].ptr + xctx->sym)->rects[PINLAYER]; p++) { /* only .node[0] ? */
if( xctx->inst[n].node && xctx->inst[n].node[p]) {
int_hash_lookup(xctx->node_redraw_table, xctx->inst[n].node[p], 0, XINSERT_NOREPLACE);
@ -357,11 +355,11 @@ void delete(void)
}
}
}
if((xctx->hilight_nets || show_pin_net_names) && xctx->sel_array[i].type == WIRE && xctx->wire[n].node) {
if((show_pin_net_names || xctx->hilight_nets) && xctx->sel_array[i].type == WIRE && xctx->wire[n].node) {
int_hash_lookup(xctx->node_redraw_table, xctx->wire[n].node, 0, XINSERT_NOREPLACE);
}
}
if((xctx->hilight_nets || show_pin_net_names)) find_inst_to_be_redrawn();
if(show_pin_net_names || xctx->hilight_nets) find_inst_to_be_redrawn();
/* already done above
@ -476,15 +474,7 @@ void delete(void)
del_rect_line_arc_poly();
update_conn_cues(0, 0);
if(xctx->hilight_nets) {
prepare_netlist_structs(0);
for(i=0; i < xctx->instances; i++) {
char *type = (xctx->inst[i].ptr+ xctx->sym)->type;
if(type && xctx->inst[i].node && IS_LABEL_SH_OR_PIN(type)) {
if(!bus_hilight_lookup( xctx->inst[i].node[0], 0, XLOOKUP)) {
xctx->inst[i].color = -10000;
}
}
}
propagate_hilights(1, 1, XINSERT_NOREPLACE);
}
xctx->lastsel = 0;
@ -636,9 +626,11 @@ void unselect_all(void)
xctx->wire[i].sel = 0;
{
if(xctx->wire[i].bus)
drawtempline(xctx->gctiled, THICK, xctx->wire[i].x1, xctx->wire[i].y1, xctx->wire[i].x2, xctx->wire[i].y2);
drawtempline(xctx->gctiled, THICK, xctx->wire[i].x1, xctx->wire[i].y1,
xctx->wire[i].x2, xctx->wire[i].y2);
else
drawtempline(xctx->gctiled, ADD, xctx->wire[i].x1, xctx->wire[i].y1, xctx->wire[i].x2, xctx->wire[i].y2);
drawtempline(xctx->gctiled, ADD, xctx->wire[i].x1, xctx->wire[i].y1,
xctx->wire[i].x2, xctx->wire[i].y2);
}
}
}

View File

@ -428,7 +428,7 @@ void spice_netlist(FILE *fd, int spice_stop )
}
my_free(952, &type);
}
if(!spice_stop && !netlist_count) redraw_hilights(); /* draw_hilight_net(1); */
if(!spice_stop && !netlist_count) redraw_hilights(0); /* draw_hilight_net(1); */
}
/* calculate the hash function relative to string s */

View File

@ -240,7 +240,7 @@ void tedax_netlist(FILE *fd, int tedax_stop )
}
my_free(967, &type);
}
if(!tedax_stop && !netlist_count) redraw_hilights(); /* draw_hilight_net(1); */
if(!tedax_stop && !netlist_count) redraw_hilights(0); /* draw_hilight_net(1); */
}

View File

@ -247,7 +247,7 @@ void check_unique_names(int rename)
bbox(END,0.0,0.0,0.0,0.0);
}
/* draw_hilight_net(1); */
redraw_hilights();
redraw_hilights(0);
/* draw_window = save_draw; */
}
@ -2878,7 +2878,7 @@ const char *translate(int inst, const char* s)
if( !pin_attr_value && !strcmp(pin_attr, "net_name")) {
char *instprop = xctx->inst[inst].prop_ptr;
char *symprop = (xctx->inst[inst].ptr + xctx->sym)->prop_ptr;
if( show_pin_net_names && (!strcmp(get_tok_value(instprop, "net_name", 0), "true") ||
if(show_pin_net_names && (!strcmp(get_tok_value(instprop, "net_name", 0), "true") ||
!strcmp(get_tok_value(symprop, "net_name", 0), "true"))) {
prepare_netlist_structs(0);
my_strdup2(1175, &pin_attr_value,

View File

@ -550,5 +550,5 @@ void verilog_netlist(FILE *fd , int verilog_stop)
my_free(1084, &type);
}
dbg(1, "verilog_netlist(): end\n");
if(!verilog_stop && !netlist_count) redraw_hilights(); /*draw_hilight_net(1); */
if(!verilog_stop && !netlist_count) redraw_hilights(0); /*draw_hilight_net(1); */
}

View File

@ -693,5 +693,5 @@ void vhdl_netlist(FILE *fd , int vhdl_stop)
my_free(1097, &type);
}
dbg(1, "vhdl_netlist(): end\n");
if(!vhdl_stop && !netlist_count) redraw_hilights(); /* draw_hilight_net(1); */
if(!vhdl_stop && !netlist_count) redraw_hilights(0); /* draw_hilight_net(1); */
}

View File

@ -333,7 +333,7 @@ typedef struct
{
unsigned short type;
int n;
unsigned short col;
unsigned int col;
} Selected;
typedef struct
@ -410,10 +410,10 @@ typedef struct
double xscale;
double yscale;
char *prop_ptr;
short layer; /* 20171201 for cairo */
int layer; /* 20171201 for cairo */
short hcenter, vcenter;
char *font; /* 20171201 for cairo */
short flags;
int flags;
} xText;
typedef struct
@ -436,7 +436,7 @@ typedef struct
char *prop_ptr;
char *type;
char *templ;
short flags; /* bit 0: embedded flag
int flags; /* bit 0: embedded flag
* bit 1: **free**
* bit 2: highight if connected wire highlighted */
} xSymbol;
@ -458,7 +458,7 @@ typedef struct
short rot;
short flip;
short sel;
short color; /* hilight color */
int color; /* hilight color */
short flags; /* bit 0: skip field,
* bit 1: flag for different textlayer for pin/labels , 1: ordinary symbol, 0: label/pin/show
* bit 2: highlight if connected net/label is highlighted */
@ -887,8 +887,8 @@ extern int text_bbox(const char * str,double xscale, double yscale,
double x1,double y1, double *rx1, double *ry1,
double *rx2, double *ry2, int *cairo_lines, int *longest_line);
extern int get_color(int value);
extern void incr_hilight_color(void);
extern void hash_inst(int what, int n);
extern void hash_inst_pin(int what, int i, int j);
extern void del_inst_table(void);
@ -1151,7 +1151,7 @@ extern void propagate_hilights(int set, int clear, int mode);
extern void select_connected_wires(int stop_at_junction);
extern void draw_hilight_net(int on_window);
extern void display_hilights(char **str);
extern void redraw_hilights(void);
extern void redraw_hilights(int clear);
extern void override_netlist_type(int type);
extern void prepare_netlist_structs(int for_netlist);
extern void create_simdata(void);