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schematic example aesthetic editings

This commit is contained in:
stefan schippers 2025-11-02 12:38:27 +01:00
parent 730b951b37
commit 1b1ea85e50
3 changed files with 14 additions and 13 deletions
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11
xschem_library/generators/test_symbolgen.sch
View File

@ -1,4 +1,4 @@
v {xschem version=3.4.4 file_version=1.2
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -23,6 +23,7 @@ G {}
K {}
V {}
S {}
F {}
E {}
B 2 20 -380 660 -110 {flags=graph
y1=0
@ -62,12 +63,10 @@ that takes a 'buf' or 'inv'
argument.} 830 -830 0 0 0.5 0.5 {}
T {Click on symbol with Control key
pressed to see the generator script} 900 -620 0 0 0.3 0.3 {}
N 30 -560 30 -520 {
N 30 -560 30 -460 {
lab=IN}
N 30 -560 110 -560 {
lab=IN}
N 30 -520 30 -460 {
lab=IN}
N 30 -460 110 -460 {
lab=IN}
N 190 -560 310 -560 {
@ -80,12 +79,10 @@ N 1000 -560 1120 -560 {
lab=IN_BUF2}
N 620 -470 620 -440 {
lab=VCC}
N 840 -560 840 -520 {
N 840 -560 840 -460 {
lab=IN}
N 840 -560 920 -560 {
lab=IN}
N 840 -520 840 -460 {
lab=IN}
N 840 -460 920 -460 {
lab=IN}
N 470 -640 520 -640 {

5
xschem_library/inst_sch_select/comp3_empty.sch
View File

@ -1,4 +1,4 @@
v {xschem version=3.4.6RC file_version=1.2
v {xschem version=3.4.8RC file_version=1.3
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
@ -23,6 +23,7 @@ G {}
K {}
V {}
S {vout out 0 2}
F {}
E {}
C {ipin.sym} 120 -550 0 0 {name=p161 lab=PLUS}
C {ipin.sym} 120 -500 0 0 {name=p1 lab=MINUS}
@ -30,5 +31,5 @@ C {opin.sym} 200 -530 0 0 {name=p20 lab=OUT}
C {noconn.sym} 200 -530 0 0 {name=l1}
C {noconn.sym} 120 -550 0 1 {name=l2}
C {noconn.sym} 120 -500 0 1 {name=l3}
C {architecture.sym} 60 -600 0 0 {code=ARCHITECTURE
C {architecture.sym} 280 -620 0 0 {code=ARCHITECTURE
"Use global schematic properties for code"}

11
xschem_library/inst_sch_select/inst_sch_select.sch
View File

@ -70,7 +70,9 @@ logx=0
logy=0
hilight_wave=-1
color="4 7"
node="plus minus"}
node="plus
minus"}
B 3 670 -620 1200 -200 {fill=0 dash=5}
T {Default instance:
Uses comp3.sch} 320 -960 0 0 0.4 0.4 { layer=7}
T {Alternate instance:
@ -102,9 +104,10 @@ referenced by a
in spice_sym_def
No schematic used} 10 -500 0 0 0.4 0.4 { layer=10}
T {Symbol based
implementation selection.} 650 -530 2 1 0.8 0.8 {}
T {The 'spice_sym_def ' attribute is defined inside the
symbol, this applies to all placements of this symbol} 640 -510 0 0 0.4 0.4 { layer=4 slant=oblique}
implementation selection.} 710 -530 2 1 0.6 0.6 {}
T {The 'spice_sym_def ' attribute is defined
inside the symbol, this applies to all
placements of this symbol} 690 -510 0 0 0.4 0.4 { layer=4 slant=oblique}
T {In all cases where an external netlist file
is provided either directly or by a .include
line xschem will adapt port order of instances