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added verilogprefix symbol attribute: will be prefixed to symbol name references in verilog netlists

This commit is contained in:
schippes 2022-11-22 16:30:59 +01:00
parent 9c31682517
commit 0d2738254a
2 changed files with 14 additions and 8 deletions
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1
src/spice_netlist.c
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@ -209,7 +209,6 @@ void global_spice_netlist(int global) /* netlister driver */
str_hash_init(&model_table, HASHSIZE); str_hash_init(&model_table, HASHSIZE);
record_global_node(2, NULL, NULL); /* delete list of global nodes */ record_global_node(2, NULL, NULL); /* delete list of global nodes */
top_sub = 0; top_sub = 0;
/* tclsetvar("spiceprefix", "1"); */
bus_char[0] = bus_char[1] = '\0'; bus_char[0] = bus_char[1] = '\0';
xctx->hiersep[0]='.'; xctx->hiersep[1]='\0'; xctx->hiersep[0]='.'; xctx->hiersep[1]='\0';
str_tmp = tclgetvar("bus_replacement_char"); str_tmp = tclgetvar("bus_replacement_char");

21
src/token.c
View File

@ -2479,9 +2479,9 @@ void print_verilog_element(FILE *fd, int inst)
int i=0, multip, tmp; int i=0, multip, tmp;
const char *str_ptr; const char *str_ptr;
const char *lab; const char *lab;
char *name=NULL; char *name=NULL, *symname = NULL;
char *generic_type=NULL; char *generic_type=NULL;
char *template=NULL,*s; char *template=NULL, *verilogprefix = NULL, *s;
int no_of_pins=0; int no_of_pins=0;
int tmp1 = 0; int tmp1 = 0;
register int c, state=TOK_BEGIN, space; register int c, state=TOK_BEGIN, space;
@ -2509,18 +2509,25 @@ void print_verilog_element(FILE *fd, int inst)
my_strdup(1562, &v_extra, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "verilog_extra", 0)); my_strdup(1562, &v_extra, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "verilog_extra", 0));
/* extra is the list of attributes NOT to consider as instance parameters */ /* extra is the list of attributes NOT to consider as instance parameters */
my_strdup(1559, &extra, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "extra", 0)); my_strdup(1559, &extra, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "extra", 0));
my_strdup(1619, &verilogprefix,
get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr, "verilogprefix", 0));
if(verilogprefix) {
my_strdup(1620, &symname, verilogprefix);
my_strcat(1621, &symname, skip_dir(xctx->inst[inst].name));
} else {
my_strdup(1622, &symname, skip_dir(xctx->inst[inst].name));
}
my_free(1624, &verilogprefix);
my_strdup(506, &template, (xctx->inst[inst].ptr + xctx->sym)->templ); my_strdup(506, &template, (xctx->inst[inst].ptr + xctx->sym)->templ);
no_of_pins= (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER]; no_of_pins= (xctx->inst[inst].ptr + xctx->sym)->rects[PINLAYER];
/* 20080915 use generic_type property to decide if some properties are strings, see later */ /* 20080915 use generic_type property to decide if some properties are strings, see later */
my_strdup(505, &generic_type, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr,"generic_type",0)); my_strdup(505, &generic_type, get_tok_value((xctx->inst[inst].ptr + xctx->sym)->prop_ptr,"generic_type",0));
s=xctx->inst[inst].prop_ptr; s=xctx->inst[inst].prop_ptr;
/* print instance subckt */ /* print instance subckt */
dbg(2, "print_verilog_element(): printing inst name & subcircuit name\n"); dbg(2, "print_verilog_element(): printing inst name & subcircuit name\n");
fprintf(fd, "%s\n", skip_dir(xctx->inst[inst].name) ); fprintf(fd, "%s\n", symname);
my_free(1623, &symname);
/* -------- print generics passed as properties */ /* -------- print generics passed as properties */
tmp=0; tmp=0;
while(1) while(1)