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update documentation for verilogprefix attr.

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stefan schippers 2022-11-22 18:09:43 +01:00
parent 1a01114af4
commit 01df7876d7
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doc/xschem_man/symbol_property_syntax.html
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@ -333,6 +333,11 @@ m5 net1 b net2 VSSPIN nlv w=wn l=ln geomod=0 m=1
<kbd>extra="VPWR VGND subckt"</kbd> since <kbd>subckt</kbd> is probably a spice attribute and you don't <kbd>extra="VPWR VGND subckt"</kbd> since <kbd>subckt</kbd> is probably a spice attribute and you don't
want it in verilog. want it in verilog.
</p> </p>
<li><kbd>verilogprefix</kbd></li>
<p>
If this attribute is defined in symbol it will be used as a prefix to the symbol name and subcircuit
expansion in verilog netlists.
</p>
<li><kbd>dir</kbd></li> <li><kbd>dir</kbd></li>
<p> <p>
Defines the direction of a symbol pin. Allowed values are <kbd>in</kbd>, <kbd>out</kbd>, <kbd>inout</kbd>. Defines the direction of a symbol pin. Allowed values are <kbd>in</kbd>, <kbd>out</kbd>, <kbd>inout</kbd>.