2023-10-09 12:49:11 +02:00
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v {xschem version=3.4.4 file_version=1.2
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*
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* This file is part of XSCHEM,
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* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
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* simulation.
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* Copyright (C) 1998-2023 Stefan Frederik Schippers
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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}
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2022-04-10 09:05:17 +02:00
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G {}
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K {}
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V {}
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S {}
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E {}
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L 8 360 -240 360 -220 {}
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L 8 340 -250 380 -250 {}
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L 8 360 -270 360 -250 {}
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P 8 5 360 -240 370 -240 360 -250 350 -240 360 -240 {fill=true}
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T {IDEAL Diode} 260 -210 0 0 0.4 0.4 {layer=8}
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N 430 -310 430 -270 {
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lab=mn}
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C {iopin.sym} 430 -150 0 0 {name=p1 lab=plus}
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C {iopin.sym} 430 -370 0 0 {name=p2 lab=minus}
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C {title.sym} 160 -40 0 0 {name=l1 author="Stefan Schippers" net_name=true}
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C {ammeter.sym} 430 -340 2 0 {name=Vm}
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C {ammeter.sym} 430 -180 2 0 {name=Vp}
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C {lab_pin.sym} 430 -210 0 1 {name=l2 sig_type=std_logic lab=pn}
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C {lab_pin.sym} 430 -290 0 1 {name=l3 sig_type=std_logic lab=mn}
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C {bsource.sym} 430 -240 2 1 {name=B1 VAR=I FUNC="'v(pn,mn) > 0 ? v(pn,mn) / Ron : v(pn,mn) / Roff'"}
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