48 lines
967 B
Systemverilog
48 lines
967 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc;
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typedef struct packed {
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logic [7:0] a;
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logic [7:0] b;
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} strp_t;
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strp_t s1;
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strp_t s2;
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strp_t s3;
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logic [7:0] alias_of_s3a;
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assign alias_of_s3a = s3.a;
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strp_t s4;
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strp_t s5;
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assign s5 = s4;
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logic [7:0] source_val;
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strp_t s6;
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assign s6.a = source_val;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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s1 <= {8'(cyc), 8'(cyc + 1)};
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s2 <= {8'(cyc + 2), 8'(cyc + 3)};
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s3 <= {8'(cyc + 4), 8'(cyc + 5)};
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s4 <= {8'(cyc + 6), 8'(cyc + 7)};
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source_val <= 8'(cyc + 8);
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s6.b <= 8'(cyc + 9);
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if (cyc == 9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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