95 lines
1.5 KiB
Plaintext
95 lines
1.5 KiB
Plaintext
$version Generated by VerilatedVcd $end
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$timescale 1ps $end
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$scope module top $end
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$var wire 1 - clk $end
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$var wire 1 . clk2 $end
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$scope module $unit $end
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$var wire 1 2 global_bit $end
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$upscope $end
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$scope module t $end
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$var wire 1 - clk $end
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$var wire 1 . clk2 $end
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$var wire 32 / cyc [31:0] $end
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$scope module v_strp $end
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$var wire 1 0 b1 $end
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$var wire 1 " b0 $end
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$upscope $end
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$scope module v_strp2 $end
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$var wire 1 1 b1 $end
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$var wire 1 # b0 $end
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$upscope $end
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$var wire 1 $ foo $end
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$var wire 8 % unpacked_array[-7] [7:0] $end
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$var wire 8 & unpacked_array[-6] [7:0] $end
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$var wire 8 ' unpacked_array[-5] [7:0] $end
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$var wire 8 ( unpacked_array[-4] [7:0] $end
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$var wire 8 ) unpacked_array[-3] [7:0] $end
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$var wire 8 * unpacked_array[-2] [7:0] $end
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$var wire 8 + unpacked_array[-1] [7:0] $end
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$var wire 8 , unpacked_array[0] [7:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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0"
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0#
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0$
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b00000000 %
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b00000000 &
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b00000000 '
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b00000000 (
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b00000000 )
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b00000000 *
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b00000000 +
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b00000000 ,
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0-
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0.
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b00000000000000000000000000000000 /
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00
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01
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02
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#10
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1$
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1-
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b00000000000000000000000000000001 /
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#15
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0-
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#20
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1"
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0$
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1-
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b00000000000000000000000000000010 /
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#25
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0-
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#30
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0"
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1$
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b00000001 ,
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1-
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b00000000000000000000000000000011 /
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#35
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0-
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#40
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1"
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0$
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1-
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b00000000000000000000000000000100 /
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#45
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0-
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#50
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0"
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1#
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1$
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b00000010 ,
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1-
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b00000000000000000000000000000101 /
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#55
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0-
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#60
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1"
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0$
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1-
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b00000000000000000000000000000110 /
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