46 lines
1.0 KiB
Systemverilog
46 lines
1.0 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test that when struct fields are driven from different clocks,
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// no trace_chg_dtype function is created (fields must be traced individually).
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bit global_bit;
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module t (clk, clk2);
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input clk;
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input clk2;
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integer cyc = 0;
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typedef struct packed {
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bit b1;
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bit b0;
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} strp_t;
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strp_t v_strp, v_strp2;
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logic foo;
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logic [7:0] unpacked_array[-7:0];
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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foo <= ~foo;
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v_strp.b0 <= cyc[0];
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v_strp2.b0 <= cyc[2];
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unpacked_array[0] = cyc[8:1];
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if (cyc == 5) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always @(posedge clk2) begin
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v_strp.b1 <= cyc[1];
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v_strp2.b1 <= cyc[3];
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for (int i = -1; i > -8; i--)
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unpacked_array[i] = cyc[7:0];
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end
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endmodule
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