30 lines
668 B
Systemverilog
30 lines
668 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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int cyc = 0;
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localparam max = 1000;
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logic [31:0] foo [max:0];
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logic [max:0] [15:0] [31:0] bar;
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always_ff @(posedge clk) begin
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cyc <= cyc + 1;
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foo[0] <= cyc;
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for (int i = 1; i <= max; i++) foo[i] <= foo[i-1];
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bar <= (bar << 32) | type(bar)'(cyc);
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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