51 lines
1.2 KiB
Systemverilog
51 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Static function call on class with parameterized extends
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0);
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// verilog_format: on
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package uvm_pkg;
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class uvm_tlm_extension #(
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type T = int
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);
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static function int ID();
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return 42;
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endfunction
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endclass
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endpackage
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import uvm_pkg::*;
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module t;
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class ext1 extends uvm_tlm_extension #(ext1);
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endclass
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class ext2 extends uvm_tlm_extension;
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endclass
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class test;
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task run_phase();
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int i, j;
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i = ext2::ID();
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`checkd(i, 42);
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j = ext1::ID();
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`checkd(j, 42);
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endtask
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endclass
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initial begin
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test tst;
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tst = new;
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tst.run_phase;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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