47 lines
986 B
Systemverilog
47 lines
986 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This files is used to generated the BLKLOOPINIT error which
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// is actually caused by not being able to unroll the for loop.
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//
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Jie Xu
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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reg [3:0] tmp[3:0];
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initial begin
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tmp[0] = 4'b0000;
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tmp[2] = 4'b0010;
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tmp[3] = 4'b0011;
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end
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// Test loop
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always @(posedge clk) begin
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int i;
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int j;
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for (i = 0; (i < 4) && (i > 1); i++) begin
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tmp[i] <= tmp[i-i];
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end
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if (tmp[0] != 4'b0000) $stop;
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if (tmp[3] != 4'b0011) $stop;
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j = 0;
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for (i = $c32("1"); i < 3; ++i) j++;
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if (j != 2) $stop;
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j = 0;
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for (i = 1; i < $c32("3"); ++i) j++;
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if (j != 2) $stop;
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j = 0;
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for (i = 1; i < 3; i = i + $c32("1")) j++;
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if (j != 2) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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