39 lines
695 B
Systemverilog
39 lines
695 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2011 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inouts
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AVDD,
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AVSS
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);
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inout AVDD;
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inout AVSS;
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sub sub ( /*AUTOINST*/
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// Inouts
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.AVDD(AVDD),
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.AVSS(AVSS)
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub ( /*AUTOARG*/
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// Inouts
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AVDD,
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AVSS
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);
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// verilator no_inline_module
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inout AVDD;
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inout AVSS;
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tri NON_IO;
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// +verilator+rand+reset+0 so z will read as zero
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initial if (NON_IO !== 'z) $stop;
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endmodule
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