26 lines
508 B
Systemverilog
26 lines
508 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Antmicro
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// SPDX-License-Identifier: CC0-1.0
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`define STRINGIFY(x) `"x`"
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module t;
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logic [128:0] x = 0;
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always #10 x = ~x;
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initial begin
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#1;
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$dumpfile(`STRINGIFY(`TEST_DUMPFILE));
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$dumpvars();
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#5;
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x = 442093479423423857275364882039482723489;
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#5;
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#100;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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