34 lines
619 B
Systemverilog
34 lines
619 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2008 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] time64;
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// Test loop
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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end
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else if (cyc < 10) begin
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end
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else if (cyc < 90) begin
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time64 = $time;
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if ($stime != time64[31:0]) $stop;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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