19 lines
446 B
Systemverilog
19 lines
446 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Srinivasan Venkataramanan
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// SPDX-License-Identifier: CC0-1.0
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module t;
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int seed = 1;
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initial begin
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seed = $get_initial_random_seed();
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$display("get_initial_random_seed=%0d", seed);
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if (seed != 22) $stop;
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$write("*-* All Finished *-*\n");
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$finish(2);
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end
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endmodule
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