17 lines
405 B
Systemverilog
17 lines
405 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic a, b, c, d;
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int delay = 1;
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// Non-constant cycle delay in sequence and/or is unsupported
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assert property (@(posedge clk) (a ##delay b) and (c ##1 d));
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endmodule
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