23 lines
425 B
Systemverilog
23 lines
425 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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logic [11:0] i;
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logic [30:0] o;
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assign o = i[31:1];
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always @(posedge clk) begin
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i = 12'h123;
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end
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always @(negedge clk) begin
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$write("Bad select %x\n", o);
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end
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endmodule
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