22 lines
502 B
Systemverilog
22 lines
502 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2015 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Outputs
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outwires,
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// Inputs
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inwires
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);
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input [7:0] inwires[12:10];
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output wire [7:0] outwires[12:10];
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assign outwires[10] = inwires[11];
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assign outwires[11] = inwires[12];
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assign outwires[12] = inwires[13]; // must be an error here
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endmodule
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