31 lines
643 B
Systemverilog
31 lines
643 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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module t;
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class uvm_built_in_comp #(
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type T = int
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);
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endclass
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class uvm_in_order_comparator #(
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type T = int,
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type comp_type = uvm_built_in_comp#(T)
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);
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endclass
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class uvm_in_order_built_in_comparator #(
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type T = int
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) extends uvm_in_order_comparator #(T);
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endclass
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initial begin
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uvm_in_order_built_in_comparator #(int) sb;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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