51 lines
1.2 KiB
Systemverilog
51 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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class Cls;
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rand real m_real;
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endclass
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module test;
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localparam LOOPS = 1000;
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int negative;
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int bitcounts[64];
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int i;
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bit [63:0] rbits;
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initial begin
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Cls c;
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c = new;
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repeat (LOOPS) begin
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i = c.randomize();
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`checkd(i, 1);
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rbits = $realtobits(c.m_real);
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`ifdef TEST_VERBOSE
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$display("%x %g", rbits, c.m_real);
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`endif
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if (c.m_real < 0) negative++;
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for (int b = 0; b < 64; ++b) begin
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if (rbits[b]) bitcounts[b]++;
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end
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end
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if (negative < LOOPS * 0.4) $error("Too few negative %0d", negative);
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for (int b = 0; b < 64; ++b) begin
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if (bitcounts[b] < LOOPS * 0.4) $error("Too few 1 bits at [%0d]: %0d", b, bitcounts[b]);
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end
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$finish;
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end
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endmodule
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