83 lines
2.2 KiB
Systemverilog
83 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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// Test that randc enum variables with user constraints only produce
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// valid enum members (not arbitrary bitvector values).
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module t;
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typedef enum bit [2:0] {
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RED = 0,
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GREEN = 1,
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BLUE = 2,
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WHITE = 3,
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BLACK = 4
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} color_t;
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class ColorClass;
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randc color_t color;
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constraint c_no_dark {color != BLACK;}
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endclass
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// Test with all enum values allowed (no exclusion constraint)
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class AllColorsClass;
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randc color_t color;
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constraint c_range {color <= WHITE;}
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endclass
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initial begin
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ColorClass c;
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AllColorsClass ac;
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int color_seen[5];
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int first_seq, all_same, this_seq;
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// Test 1: randc enum with exclusion constraint
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// Values must be valid enum members (0-4) and not BLACK (4)
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c = new;
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repeat (40) begin
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`checkd(c.randomize(), 1);
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`checkd(c.color <= BLACK, 1);
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`checkd(c.color == BLACK, 0);
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end
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// Test 2: randc enum with range constraint - run multiple trials,
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// verify only valid enum members produced and sequence varies
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all_same = 1;
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first_seq = 0;
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for (int trial = 0; trial < 3; trial++) begin
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ac = new;
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this_seq = 0;
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for (int j = 0; j < 4; j++) color_seen[j] = 0;
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repeat (40) begin
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`checkd(ac.randomize(), 1);
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`checkd(ac.color <= WHITE, 1);
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color_seen[ac.color] = 1;
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end
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// Record first 4 values for sequence comparison
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repeat (4) begin
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`checkd(ac.randomize(), 1);
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this_seq = this_seq * 8 + int'(ac.color);
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end
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`checkd(color_seen[0], 1);
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`checkd(color_seen[1], 1);
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`checkd(color_seen[2], 1);
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`checkd(color_seen[3], 1);
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if (trial == 0) first_seq = this_seq;
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else if (this_seq != first_seq) all_same = 0;
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end
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`checkd(all_same, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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