46 lines
942 B
Systemverilog
46 lines
942 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Issue #7195
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module t;
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class uvm_reg;
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endclass
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class reg_slave_DATA extends uvm_reg;
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endclass
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class reg_slave_TABLES extends uvm_reg;
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function uvm_reg create(string name = "");
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reg_slave_TABLES tmp;
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tmp = new;
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return tmp;
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endfunction
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endclass
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class reg_block_slave;
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reg_slave_DATA DATA;
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rand reg_slave_TABLES TABLES[4];
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virtual function void build();
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foreach (TABLES[i]) TABLES[i] = new;
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this.configure(TABLES); // Issue was here
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endfunction
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function void configure(uvm_reg reg_a[]);
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foreach (reg_a[i]) $display("%p", reg_a[i]);
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endfunction
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endclass
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initial begin
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reg_block_slave c;
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c = new;
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c.build;
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$finish;
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end
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endmodule
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