19 lines
418 B
Systemverilog
19 lines
418 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2025 Antmicro Ltd
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// SPDX-License-Identifier: CC0-1.0
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`timescale 1ns/1ps
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module top(/*AUTOARG*/
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input logic clk,
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input logic rst,
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output logic top_out
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);
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submod u_submod (/*AUTOINST*/
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.clk (clk),
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.rst (rst),
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.out_signal(top_out)
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);
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endmodule
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