53 lines
983 B
Systemverilog
53 lines
983 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2005 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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parameter PAR = 3;
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m3 m3_inst (.clk(clk));
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defparam m3_inst.FROMDEFP = 19; defparam m3_inst.P2 = 2;
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//defparam m3_inst.P3 = PAR;
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defparam m3_inst.P3 = 3;
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integer cyc = 1;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 1) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module m3 (
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input clk
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);
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localparam LOC = 13;
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parameter UNCH = 99;
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parameter P1 = 10;
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parameter P2 = 20;
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parameter P3 = 30;
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parameter FROMDEFP = 11;
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initial begin
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$display("%x %x %x", P1, P2, P3);
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end
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always @(posedge clk) begin
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if (UNCH !== 99) $stop;
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if (P1 !== 10) $stop;
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if (P2 !== 2) $stop;
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if (P3 !== 3) $stop;
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if (FROMDEFP !== 19) $stop;
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end
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endmodule
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