32 lines
543 B
Systemverilog
32 lines
543 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t ( /*AUTOARG*/
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// Inputs
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a,
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y
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);
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input [1:0] a;
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output [3:0] y;
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Test #(.C(2)) test (.*);
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endmodule
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module Test #(
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C = 3,
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localparam O = 1 << C
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) (
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input [C-1:0] a,
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output reg [O-1:0] y
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);
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initial begin
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if (O != 4) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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