52 lines
1.2 KiB
Systemverilog
52 lines
1.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2016 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// verilog_format: off
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
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// verilog_format: on
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module t ( /*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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sub #(
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.IDX(0),
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.CHK(10)
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) i0 ();
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sub #(
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.IDX(2),
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.CHK(12)
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) i2 ();
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sub #(
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.IDX(7),
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.CHK(17)
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) i7 ();
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always @(posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module sub ();
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function integer get_element;
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input integer index;
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input integer array_arg[7:0];
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get_element = array_arg[index];
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endfunction
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parameter integer IDX = 5;
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parameter integer CHK = 5;
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localparam integer array[0:7] = '{10, 11, 12, 13, 14, 15, 16, 17};
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localparam element1 = array[IDX];
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localparam elementf = get_element(IDX, array);
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initial begin
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`checkh(element1, CHK);
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`checkh(elementf, CHK);
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end
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endmodule
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