21 lines
483 B
Systemverilog
21 lines
483 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input logic [7:0] i1[8],
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input logic [7:0] i2[16],
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input logic [7:0] i3[512],
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output logic [7:0] o1[8],
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output logic [7:0] o2[16],
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output logic [7:0] o3[256]
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);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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