119 lines
3.2 KiB
Systemverilog
119 lines
3.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2005 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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//
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// Example module to create problem.
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//
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// generate a 64 bit value with bits
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// [HighMaskSel_Bot : LowMaskSel_Bot ] = 1
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// [HighMaskSel_Top+32: LowMaskSel_Top+32] = 1
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// all other bits zero.
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module t (
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input clk
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);
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integer cyc;
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initial cyc = 0;
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reg [7:0] crc;
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reg [63:0] sum;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [63:0] HighLogicImm; // From example of example.v
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wire [63:0] LogicImm; // From example of example.v
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wire [63:0] LowLogicImm; // From example of example.v
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// End of automatics
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wire [5:0] LowMaskSel_Top = crc[5:0];
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wire [5:0] LowMaskSel_Bot = crc[5:0];
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wire [5:0] HighMaskSel_Top = crc[5:0] + {4'b0, crc[7:6]};
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wire [5:0] HighMaskSel_Bot = crc[5:0] + {4'b0, crc[7:6]};
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example example ( /*AUTOINST*/
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// Outputs
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.LogicImm(LogicImm[63:0]),
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.LowLogicImm(LowLogicImm[63:0]),
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.HighLogicImm(HighLogicImm[63:0]),
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// Inputs
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.LowMaskSel_Top(LowMaskSel_Top[5:0]),
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.HighMaskSel_Top(HighMaskSel_Top[5:0]),
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.LowMaskSel_Bot(LowMaskSel_Bot[5:0]),
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.HighMaskSel_Bot(HighMaskSel_Bot[5:0])
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);
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always @(posedge clk) begin
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cyc <= cyc + 1;
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crc <= {crc[6:0], ~^{crc[7], crc[5], crc[4], crc[3]}};
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n", $time, cyc, crc, LowMaskSel_Top,
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HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot, LowLogicImm, HighLogicImm, LogicImm);
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`endif
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if (cyc == 0) begin
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// Single case
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crc <= 8'h0;
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sum <= 64'h0;
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end
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else if (cyc == 1) begin
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// Setup
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crc <= 8'hed;
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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sum <= {sum[62:0], sum[63]} ^ LogicImm;
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%b %x\n", $time, cyc, crc, sum);
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if (crc !== 8'b00111000) $stop;
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if (sum !== 64'h58743ffa61e41075) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module example ( /*AUTOARG*/
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// Outputs
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LogicImm,
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LowLogicImm,
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HighLogicImm,
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// Inputs
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LowMaskSel_Top,
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HighMaskSel_Top,
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LowMaskSel_Bot,
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HighMaskSel_Bot
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);
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input [5:0] LowMaskSel_Top, HighMaskSel_Top;
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input [5:0] LowMaskSel_Bot, HighMaskSel_Bot;
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output [63:0] LogicImm;
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output [63:0] LowLogicImm, HighLogicImm;
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wire [63:0] LowLogicImm, HighLogicImm;
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/* verilator lint_off UNSIGNED */
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/* verilator lint_off CMPCONST */
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genvar i;
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generate
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for (i = 0; i < 64; i = i + 1) begin : MaskVal
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if (i >= 32) begin
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assign LowLogicImm[i] = (LowMaskSel_Top <= i[5:0]);
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assign HighLogicImm[i] = (HighMaskSel_Top >= i[5:0]);
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end
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else begin
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assign LowLogicImm[i] = (LowMaskSel_Bot <= i[5:0]);
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assign HighLogicImm[i] = (HighMaskSel_Bot >= i[5:0]);
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end
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end
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endgenerate
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/* verilator lint_on UNSIGNED */
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/* verilator lint_on CMPCONST */
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assign LogicImm = LowLogicImm & HighLogicImm;
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endmodule
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