87 lines
1.5 KiB
Systemverilog
87 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2013 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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`ifdef INLINE_A //verilator inline_module
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`else //verilator no_inline_module
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`endif
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// verilog_format: off
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bmod bsub3 (.clk, .n(3));
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bmod bsub2 (.clk, .n(2));
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bmod bsub1 (.clk, .n(1));
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bmod bsub0 (.clk, .n(0));
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// verilog_format: on
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endmodule
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module bmod (
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input clk,
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input [31:0] n
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);
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`ifdef INLINE_B //verilator inline_module
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`else //verilator no_inline_module
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`endif
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cmod csub (
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.clk,
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.n
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);
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endmodule
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module cmod (
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input clk,
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input [31:0] n
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);
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`ifdef INLINE_C //verilator inline_module
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`else //verilator no_inline_module
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`endif
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reg [31:0] clocal;
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always @(posedge clk) clocal <= n;
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dmod dsub (
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.clk,
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.n
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);
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endmodule
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module dmod (
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input clk,
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input [31:0] n
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);
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`ifdef INLINE_D //verilator inline_module
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`else //verilator no_inline_module
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`endif
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reg [31:0] dlocal;
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always @(posedge clk) dlocal <= n;
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int cyc;
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always @(posedge clk) begin
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cyc <= cyc + 1;
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end
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always @(posedge clk) begin
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if (cyc > 10) begin
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`ifdef TEST_VERBOSE
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$display("%m: csub.clocal=%0d dlocal=%0d", csub.clocal, dlocal);
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`endif
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if (csub.clocal !== n) $stop;
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if (dlocal !== n) $stop;
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end
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if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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