95 lines
2.2 KiB
Systemverilog
95 lines
2.2 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2022 Varun Koyyalagunta
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {logic x;} nested_named_t;
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typedef struct packed {
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struct packed {logic x;} nested_anonymous;
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nested_named_t nested_named;
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logic [1:0] x;
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} nibble_t;
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module t (
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input clk
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);
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integer cyc = 0;
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logic [63:0] crc;
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logic [63:0] sum;
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// Take CRC data and apply to testblock inputs
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nibble_t [7:0] in;
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assign in = crc[31:0];
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nibble_t [7:0] out;
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Test test (
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.out0({out[1], out[0]}),
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.out1({{out[5], out[4]}, {out[3], out[2]}}),
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.out2(out[6]),
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.out3(out[7]),
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.clk(clk),
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.in0(in[0]),
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.in1(in[1]),
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.in2({in[5], in[4], in[3], in[2]}),
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.in3({in[7], in[6]})
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);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {32'h0, out};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc < 10) begin
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sum <= '0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h4afe43fb79d7b71e
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (
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// Outputs
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output nibble_t [1:0] out0,
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output nibble_t [1:0] out1[2],
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output nibble_t out2,
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output nibble_t out3,
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// Inputs
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input clk,
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input nibble_t in0,
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input nibble_t in1,
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input nibble_t [3:0] in2,
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input nibble_t in3[2]
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); /*verilator hier_block*/
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always @(posedge clk) begin
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{out3, out2, out1[0], out1[1], out0} <= {in3[0], in3[1], in2, in1, in0};
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end
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endmodule
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