117 lines
2.8 KiB
Systemverilog
117 lines
2.8 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2009 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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`define DDIFF_BITS 9
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`define AOA_BITS 8
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`define HALF_DDIFF `DDIFF_BITS'd256
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`define MAX_AOA `AOA_BITS'd255
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`define BURP_DIVIDER 9'd16
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module t (
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input clk
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);
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integer cyc = 0;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [`DDIFF_BITS-1:0] DDIFF_B = crc[`DDIFF_BITS-1:0];
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wire reset = (cyc < 7);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [`AOA_BITS-1:0] AOA_B; // From test of Test.v
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// End of automatics
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Test test ( /*AUTOINST*/
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// Outputs
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.AOA_B(AOA_B[`AOA_BITS-1:0]),
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// Inputs
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.DDIFF_B(DDIFF_B[`DDIFF_BITS-1:0]),
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.reset(reset),
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.clk(clk)
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);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {56'h0, AOA_B};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= 64'h0;
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end
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else if (cyc < 10) begin
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sum <= 64'h0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h3a74e9d34771ad93
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test ( /*AUTOARG*/
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// Outputs
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AOA_B,
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// Inputs
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DDIFF_B,
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reset,
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clk
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);
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input [`DDIFF_BITS-1:0] DDIFF_B;
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input reset;
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input clk;
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output reg [`AOA_BITS-1:0] AOA_B;
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reg [`AOA_BITS-1:0] AOA_NEXT_B;
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reg [`AOA_BITS-1:0] tmp;
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always @(posedge clk) begin
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if (reset) begin
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AOA_B <= 8'h80;
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end
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else begin
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AOA_B <= AOA_NEXT_B;
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end
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end
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always @* begin
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// verilator lint_off WIDTH
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tmp = ((`HALF_DDIFF - DDIFF_B) / `BURP_DIVIDER);
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t_aoa_update(AOA_NEXT_B, AOA_B, ((`HALF_DDIFF - DDIFF_B) / `BURP_DIVIDER));
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// verilator lint_on WIDTH
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end
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task t_aoa_update;
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output [`AOA_BITS-1:0] aoa_reg_next;
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input [`AOA_BITS-1:0] aoa_reg;
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input [`AOA_BITS-1:0] aoa_delta_update;
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begin
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if ((`MAX_AOA - aoa_reg) < aoa_delta_update) //Overflow protection
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aoa_reg_next = `MAX_AOA;
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else aoa_reg_next = aoa_reg + aoa_delta_update;
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end
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endtask
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endmodule
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