53 lines
991 B
Systemverilog
53 lines
991 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2017 Todd Strader
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// SPDX-License-Identifier: CC0-1.0
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function integer f_add(input [31:0] a, input [31:0] b);
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f_add = a + b;
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if (f_add == 15) $fatal(2, "f_add = 15");
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endfunction
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// Speced ok: function called from function
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function integer f_add2(input [31:0] a, input [31:0] b, input [31:0] c);
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f_add2 = f_add(a, b) + c;
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endfunction
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module c9 #(
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parameter A = 1,
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parameter B = 1
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);
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localparam SOMEP = f_add2(A, B, 9);
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endmodule
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module b8 #(
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parameter A = 1
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);
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c9 #(
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.A(A),
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.B(8)
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) c9 ();
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endmodule
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module t;
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localparam P6 = f_add(5, 1);
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localparam P14 = f_add2(2, 3, f_add(4, 5));
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//localparam P24 = f_add2(7, 8, 9);
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b8 b8 ();
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b8 #(.A(6)) b8_a6 ();
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b8 #(.A(7)) b8_a7 ();
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initial begin
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// Should never get here
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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