43 lines
812 B
Systemverilog
43 lines
812 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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interface Ifc;
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task run;
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endtask
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int data = 0;
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endinterface
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program Prog;
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task run;
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endtask
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int data = 0;
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endprogram
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module Inner;
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task run;
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endtask
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endmodule
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module Outer;
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Inner inner();
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endmodule
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module t;
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Ifc ifc1();
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Prog prog1();
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Outer outer1();
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initial begin
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disable ifc1.missing_task;
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disable prog1.missing_task;
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disable outer1.inner.missing_task;
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disable ifc1.data;
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disable prog1.data;
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end
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endmodule
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