30 lines
491 B
Systemverilog
30 lines
491 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module top (
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input wire clk
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);
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logic [1:0][31:0] i;
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logic o;
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always @(posedge clk) begin
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force i = 64'hFFFFFFFF_FFFFFFFF;
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end
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sub sub_i (
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.i(i),
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.o(o)
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);
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endmodule
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module sub (
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input logic [63:0] i,
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output logic o
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);
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assign o = |i;
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endmodule
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