45 lines
801 B
Systemverilog
45 lines
801 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2023 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc;
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bit a;
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bit b;
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// Test loop
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always @(posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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a <= '0;
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b <= '0;
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end
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else if (cyc == 10) begin
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a <= '1;
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b <= '1;
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end
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else if (cyc == 11) begin
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a <= '0;
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b <= '1;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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always_ff @(posedge clk) begin
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C1 :
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cover property (a) begin
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// Assert under cover legal in some other simulators
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A2 : assert (b);
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end
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end
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endmodule
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