17 lines
323 B
Systemverilog
17 lines
323 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2020 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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class Cls #(
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parameter PARAM = 12
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);
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endclass
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module t;
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Cls #(.PARAM($random)) c; // Bad param name
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endmodule
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