100 lines
2.3 KiB
Systemverilog
100 lines
2.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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int cyc;
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reg [63:0] crc;
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reg [63:0] sum;
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// Take CRC data and apply to testblock inputs
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wire [9:0] a0 = crc[9:0];
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wire [9:0] a1 = crc[19:10];
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wire [9:0] b1 = crc[39:30];
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wire asel = crc[62];
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wire bsel = crc[63];
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [9:0] aq; // From test of Test.v
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wire [9:0] bq; // From test of Test.v
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// End of automatics
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Test test ( /*AUTOINST*/
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// Outputs
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.aq(aq[9:0]),
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.bq(bq[9:0]),
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// Inputs
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.a0(a0[9:0]),
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.a1(a1[9:0]),
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.b1(b1[9:0]),
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.asel(asel),
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.bsel(bsel)
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);
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// Aggregate outputs into a single result vector
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wire [63:0] result = {44'h0, aq, bq};
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// Test loop
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result);
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`endif
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cyc <= cyc + 1;
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crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
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sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]};
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if (cyc == 0) begin
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// Setup
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crc <= 64'h5aef0c8d_d70a4497;
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sum <= '0;
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end
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else if (cyc < 10) begin
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sum <= '0;
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end
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else if (cyc < 90) begin
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end
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else if (cyc == 99) begin
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$write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h2c5e6c5e285efafa
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module Test (
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input [9:0] a0,
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input [9:0] a1,
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input [9:0] b1,
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input asel,
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input bsel,
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output wire [9:0] aq,
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output wire [9:0] bq
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);
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assign aq = MUX10_2(a0, a1, asel);
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assign bq = MUX10_2(aq, b1, bsel);
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function [9:0] MUX10_2; // Legacy code - not function automatic
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input [9:0] i0;
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input [9:0] i1;
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input [0:0] sel;
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/*static*/ logic [9:0] result; // Note this is not automatic
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case (sel)
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1'b0: result = i0;
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default: result = i1;
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endcase
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MUX10_2 = result;
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endfunction
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endmodule
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