57 lines
1.1 KiB
Systemverilog
57 lines
1.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2019 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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//bug1604
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module t ( /*AUTOARG*/
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// Outputs
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two,
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// Inputs
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clk,
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aresetn,
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ten
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);
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input wire clk;
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input wire aresetn;
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input reg [9:0] ten;
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output reg [1:0] two;
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// Passes with this
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//output reg [1:0] rx;
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//output reg [1:0] ry;
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function [1:0] func(input [1:0] p0_x, input [1:0] p0_y, input [1:0] p1_x, input [1:0] p1_y,
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input [1:0] sel);
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reg [1:0] rx;
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reg [1:0] ry;
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`ifdef NOT_DEF
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// This way works
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rx = sel == 2'b10 ? p1_x : p0_x;
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ry = sel == 2'b10 ? p1_y : p0_y;
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`else
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// This way fails to compile
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if (sel == 2'b10) begin
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rx = p1_x;
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ry = p1_y;
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end
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else begin
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rx = p0_x;
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ry = p0_y;
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end
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`endif
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// Note rx and ry are unused
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//func = rx | ry; // Also passes
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func = 0;
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endfunction
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always @(*) begin
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two = func(ten[8+:2], ten[6+:2], ten[4+:2], ten[2+:2], ten[0+:2]);
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end
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endmodule
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