20 lines
389 B
Systemverilog
20 lines
389 B
Systemverilog
// DESCRIPTION: Verilator: Test X/Z four-state simulation with --x-sim
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//
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// SPDX-FileCopyrightText: 2026
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// SPDX-License-Identifier: LGPL-3.0-only
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module t;
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reg [3:0] a = 4'bXXXX;
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reg [3:0] b = 4'b1010;
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reg [3:0] y_and;
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initial begin
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y_and = a & b;
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$display("a = %b", a);
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$display("b = %b", b);
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$display("a & b = %b", y_and);
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$finish;
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end
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endmodule
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