99 lines
3.1 KiB
Systemverilog
99 lines
3.1 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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// Test: System functions ($onehot, $onehot0, $countbits, $clog2) inside
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// constraint blocks (IEEE 1800-2017 Section 18.5.12)
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class test_onehot;
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rand bit [7:0] value;
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constraint c_hot {$onehot(value);}
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endclass
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class test_onehot0;
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rand bit [7:0] value;
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constraint c_hot0 {$onehot0(value);}
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endclass
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class test_countbits_ones;
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rand bit [7:0] value;
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constraint c_bits {$countbits(value, '1) == 3;}
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endclass
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class test_countbits_zeros;
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rand bit [7:0] value;
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constraint c_bits {$countbits(value, '0) == 6;} // 6 zeros = 2 ones
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endclass
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class test_clog2;
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rand bit [7:0] data_width;
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rand bit [7:0] addr_bits;
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constraint c_log {addr_bits == 8'($clog2(data_width));}
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constraint c_nonzero {data_width > 0;}
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endclass
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module t;
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initial begin
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automatic test_onehot oh = new;
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automatic test_onehot0 oh0 = new;
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automatic test_countbits_ones cb1 = new;
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automatic test_countbits_zeros cb0 = new;
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automatic test_clog2 cl = new;
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automatic bit ok = 1'b1;
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// Test $onehot: exactly one bit set
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repeat (20) begin
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if (oh.randomize() == 0) $fatal(1, "$onehot randomize failed");
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if ($onehot(oh.value) !== 1'b1) begin
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$display("FAIL: $onehot value=%08b, $onehot=%0b", oh.value, $onehot(oh.value));
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ok = 1'b0;
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end
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end
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// Test $onehot0: zero or one bit set
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repeat (20) begin
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if (oh0.randomize() == 0) $fatal(1, "$onehot0 randomize failed");
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if ($onehot0(oh0.value) !== 1'b1) begin
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$display("FAIL: $onehot0 value=%08b, $onehot0=%0b", oh0.value, $onehot0(oh0.value));
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ok = 1'b0;
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end
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end
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// Test $countbits counting ones: exactly 3 ones
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repeat (20) begin
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if (cb1.randomize() == 0) $fatal(1, "$countbits('1) randomize failed");
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if ($countbits(cb1.value, '1) != 3) begin
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$display("FAIL: $countbits('1) value=%08b, count=%0d", cb1.value, $countbits(cb1.value,
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'1));
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ok = 1'b0;
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end
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end
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// Test $countbits counting zeros: exactly 6 zeros (= 2 ones)
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repeat (20) begin
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if (cb0.randomize() == 0) $fatal(1, "$countbits('0) randomize failed");
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if ($countbits(cb0.value, '0) != 6) begin
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$display("FAIL: $countbits('0) value=%08b, zeros=%0d ones=%0d", cb0.value,
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$countbits(cb0.value, '0), $countbits(cb0.value, '1));
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ok = 1'b0;
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end
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end
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// Test $clog2: addr_bits == $clog2(data_width)
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repeat (20) begin
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if (cl.randomize() == 0) $fatal(1, "$clog2 randomize failed");
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if (cl.addr_bits != 8'($clog2(cl.data_width))) begin
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$display("FAIL: $clog2 data_width=%0d, addr_bits=%0d, expected=%0d", cl.data_width,
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cl.addr_bits, $clog2(cl.data_width));
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ok = 1'b0;
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end
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end
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if (ok) $display("All tests passed");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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