30 lines
595 B
Systemverilog
30 lines
595 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2024 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// Test that item.index in array reduction constraints is not yet supported
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class Packet;
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rand bit [3:0] data[5];
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constraint c {
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// This should trigger unsupported warning
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data.sum() with (item.index) <= 10;
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}
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endclass
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module t;
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initial begin
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Packet p;
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int i;
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p = new;
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i = p.randomize();
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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