28 lines
829 B
Systemverilog
28 lines
829 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2026 PlanV GmbH
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// SPDX-License-Identifier: CC0-1.0
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module t (input clk);
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logic a, b;
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// === Consecutive repetition [*N] unsupported forms ===
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// Unsupported: non-##1 inter-repetition delay
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assert property (@(posedge clk) a [*2] ##3 b);
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// Unsupported: standalone range repetition (no ## anchor)
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assert property (@(posedge clk) a [*2:3] |-> 1);
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// Unsupported: trailing consecutive repetition in sequence
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assert property (@(posedge clk) b ##1 a[+]);
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// === Nonconsecutive repetition [=N] unsupported forms ===
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// Unsupported: nonconsecutive rep inside throughout
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assert property (@(posedge clk) a throughout (b[=2]))
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else $error("FAIL");
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endmodule
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