39 lines
727 B
Systemverilog
39 lines
727 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2025 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package uvm_pkg;
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virtual class uvm_sequence #(
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type REQ = int
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);
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endclass
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class uvm_sequence_library #(
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type REQ = int
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) extends uvm_sequence #(REQ);
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randc bit [15:0] select_randc; // Passes without randc here
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task body();
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if (0 == randomize(select_randc)) begin
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end
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endtask
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endclass
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endpackage
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module t;
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import uvm_pkg::*;
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class t1 extends uvm_sequence_library;
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endclass
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initial begin
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t1 c;
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c = new;
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c.body;
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$finish;
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end
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endmodule
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