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29 lines
642 B
Systemverilog
29 lines
642 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2026 by Verilator Authors.
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// SPDX-FileCopyrightText: 2026 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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// A parameterized class nested in a specialized parameterized interface must
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// produce distinct, well-formed class-package names during C++ emission.
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interface intf #(
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int P = 1
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);
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class Cls #(
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int Q
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);
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endclass
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Cls #(P) obj;
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endinterface
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module t;
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intf #(2) intf_i ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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