Files
verilator/docs
Geza Lore ba893abb2c Optimize circular logic in Dfg (#7902)
Introduce a new DfgPrev vertex, representing the value of a variable
before any in-graph assignments. This can be used to break all remaining
cycles in the graph, so all Dfgs become acyclic after V3DfgBreakCycles.
The circular dataflow is still represented, and is taken care of by the
scheduler, it is just the DfgGraph that represents the logic that
becomes acyclic.

This makes V3DfgBreakCycles a mandatory transform, so drop the disabling
-fno-dfg-break-cycles option (still parsed, but has no effect).

Note the effect of this is small, as most cycles can be fixed up by
driver tracing, which is unchanged, but this is required for some
upcoming work.
2026-08-18 14:54:12 +02:00
..
2022-05-14 16:12:57 -04:00
2026-06-15 17:44:50 -04:00
2026-08-11 20:05:01 -04:00

..
   SPDX-FileCopyrightText: 2003-2026 Wilson Snyder
   SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0

Verilator Documentation
=======================

This folder contains sources for Verilator documentation.

For formatted documentation see:

- `Verilator README <https://github.com/verilator/verilator>`_

- `Verilator installation and package directory structure
  <https://verilator.org/install>`_

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  `Verilator manual (PDF) <https://verilator.org/verilator_doc.pdf>`_

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