39 lines
883 B
Systemverilog
39 lines
883 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain.
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// SPDX-FileCopyrightText: 2016 Wilson Snyder
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// SPDX-License-Identifier: CC0-1.0
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module t (
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input clk
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);
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typedef struct packed {
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logic [2:0] _foo;
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logic [2:0] _bar;
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} struct_t;
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logic [2:0] meh;
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struct_t param;
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localparam integer TWENTYONE = 21;
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// verilator lint_off WIDTH
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assign param = '{_foo: TWENTYONE % 8 + 1, _bar: (TWENTYONE / 8) + 1};
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assign meh = TWENTYONE % 8 + 1;
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// verilator lint_on WIDTH
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always @(posedge clk) begin
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`ifdef TEST_VERBOSE
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$display("param: %d, %d, %b, %d", param._foo, param._bar, param, meh);
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`endif
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if (param._foo != 6) $stop;
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if (param._bar != 3) $stop;
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if (param != 6'b110011) $stop;
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if (meh != 6) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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