80 lines
1.5 KiB
Systemverilog
80 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This program is free software; you can redistribute it and/or modify it
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// under the terms of either the GNU Lesser General Public License Version 3
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// or the Perl Artistic License Version 2.0.
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// SPDX-FileCopyrightText: 2022 Geza Lore
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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// This hits a case where parameter specialization of recursive modules
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// used to yield a module list that was not topologically sorted, which
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// then caused V3Inline to blow up as it assumes that.
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module top #(
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parameter N = 8
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) (
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input wire [N-1:0] i,
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output wire [N-1:0] o,
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output wire [N-1:0] a
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);
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sub #(
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.N(N)
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) inst (
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.i(i),
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.o(a)
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);
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generate
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if (N > 1) begin : recursive
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top #(
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.N(N / 2)
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) hi (
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.i(i[N-1:N/2]),
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.o(o[N-1:N/2]),
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.a()
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);
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top #(
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.N(N / 2)
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) lo (
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.i(i[N/2-1:0]),
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.o(o[N/2-1:0]),
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.a()
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);
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end
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else begin : base
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assign o = i;
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end
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endgenerate
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endmodule
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module sub #(
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parameter N = 8
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) (
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input wire [N-1:0] i,
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output wire [N-1:0] o
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);
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generate
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if (N > 1) begin : recursive
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sub #(
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.N(N / 2)
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) hi (
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.i(i[N-1:N/2]),
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.o(o[N-1:N/2])
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);
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sub #(
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.N(N / 2)
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) lo (
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.i(i[N/2-1:0]),
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.o(o[N/2-1:0])
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);
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end
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else begin : base
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assign o = i;
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end
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endgenerate
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endmodule
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